A.2. CoreSight DAP signals

Table A.1 shows the CoreSight Debug Access Port (DAP) signals.

Table A.1. CoreSight DAP signals

NameTypeDescriptionClock domain
CDBGPWRUPACKInput

Debug Power Domain power-up acknowledge

SWJ-DP

None
CDBGPWRUPREQOutput

Debug Power Domain power-up request

SWJ-DP

None
CDBGRSTACKInput

Debug reset acknowledge from reset controller

SWJ-DP

None
CDBGRSTREQOutput

Debug reset request to reset controller

SWJ-DP

None
CSRTCK[7:0] Input

Return DBGCLK from JTAG slaves

JTAG-AP

None
CSTCK[7:0]Output

DBGCLK to JTAG slaves

JTAG-AP

PCLKDBG
CSTDI[7:0]Output

TDI to JTAG slaves

JTAG-AP

PCLKDBG
CSTDO[7:0] Input

TDO from JTAG slaves

JTAG-AP

PCLKDBG
CSTMS[7:0]Output

TMS to JTAG slaves

JTAG-AP

PCLKDBG
CSYSPWRUPACKInput

System Power Domain power-up acknowledge

SWJ-DP

None
CSYSPWRUPREQOutput

System Power Domain power-up request

SWJ-DP

None
DAPABORTOutput

DAP Abort, to support Cortex-M3 processor

DAPBUS exported interface

DAPCLK
DAPADDR[31:0]Output

DAP Address, to support Cortex-M3 processor

DAPBUS exported interface

DAPCLK
DAPENABLEOutput

DAP Enable Transaction, to support Cortex-M3 processor

DAPBUS exported interface

DAPCLK
DAPRDATACM3[31:0]Input

DAP Read Data from Cortex-M3 processor

DAPBUS exported interface

DAPCLK
DAPREADYCM3Input

DAP Data Bus Ready from Cortex-M3 processor

DAPBUS exported interface

DAPCLK
DAPSELCM3Output

DAP transaction select to Cortex-M3 processor

DAPBUS exported interface

DAPCLK
DAPSLVERRCM3Input

AP slave error response from Cortex-M3 processor

DAPBUS exported interface

DAPCLK
DAPWDATA[31:0]Output

DAP Write Data, to support Cortex-M3 processor

DAPBUS exported interface

DAPCLK
DAPWRITEOutput

DAP Bus Write, to support Cortex-M3 processor

DAPBUS exported interface

DAPCLK
DBGENInput

Invasive Debug enable, enables AHB transfers

AHB-AP

None
DEVICEENInput

Enable access to Debug APB from the DAP

APB-AP

None
HADDRM[31:0]Output

AHB master address

AHB-AP

HCLK
HBSTRBM[3:0] Output

AHB master byte lane strobes

AHB-AP

HCLK
HBURSTM[2:0] Output

AHB master burst type, always SINGLE

AHB-AP

HCLK
HCLKInput

AHB clock

AHB-AP

N/A
HCLKENInput

AHB clock enable term

AHB-AP

HCLK
HLOCKMOutput

AHB master requires locked access to the bus, always zero

AHB-AP

HCLK
HPROTM[6:0] Output

AHB master privilege information

AHB-AP

HCLK
HRDATAM[31:0] InputAHB master read data AHB-APHCLK
HREADYMInput

AHB ready response to master port

AHB-AP

HCLK
HRESETnInput

AHB reset

AHB-AP

HCLK
HRESPM[1:0] Input

AHB transfer response to master port

AHB-AP

HCLK
HSIZEM[2:0]Output

AHB master transfer size

AHB-AP

HCLK
HTRANSM[1:0]Output

AHB master transfer type, IDLE or NONSEQ

AHB-AP

HCLK
HWDATAM[31:0] Output

AHB master write data

AHB-AP

HCLK
HWRITEMOutput

AHB master transfer direction

AHB-AP

HCLK
INSTANCEID[3:0]Input

Distinguishes between multiple instances of the same part, see Instance ID

SWJ-DP

SWCLKTCK
JTAGNSWOutputHIGH if JTAG selected, LOW if SWD selectedSWCLKTCK
JTAGTOPOutput

JTAG state machine is in one of the top four modes:

  • Test-Logic-Reset

  • Run-Test/Idle

  • Select-DR-Scan

  • Select-IR-Scan.

SWCLKTCK
nCDBGPWRDNInputDebug infrastructure power-down controlNone
nCSOCPWRDNInputExternal system, SOC domain, power-down controlNone
nCSTRST[7:0] Output

nTRST to JTAG slaves

JTAG-AP

PCLKDBG
nPOTRSTInput

Power-on reset

SWJ-DP

SWCLKTCK
nSRSTOUT[7:0] Output

Subsystem reset to JTAG slaves

JTAG-AP

PCLKDBG
nTDOENOutput

TAP Data Out Enable

SWJ-DP

SWCLKTCK
nTRST Input

TAP Reset, Asynchronous

SWJ-DP

SWCLKTCK
PADDRDBG[31:2]Output

Debug APB address bus

APB-Mux

PCLKDBG
PADDRSYS[30:2]Input

System APB address bus

APB-Mux

PCLKSYS
PCLKDBGInputDebug APB clockN/A
PCLKENDBGInputDebug APB clock enablePCLKDBG
PCLKENSYSInput

System APB clock enable

APB-Mux

PCLKSYS
PCLKSYSInput

System APB clock, typically HCLK

APB-Mux

PCLKSYS
PENABLEDBGOutput

Debug APB enable signal, indicates second and subsequent cycles

APB-Mux

PCLKDBG
PENABLESYSInput

System APB enable signal, indicates second and subsequent cycles

APB-Mux

PCLKSYS
PORTCONNECTED[7:0]Input

JTAG ports are connected, static signals

JTAG-AP

PCLKDBG
PORTENABLED[7:0]Input

JTAG ports are active

JTAG-AP

PCLKDBG
PRDATADBG[31:0]InputDebug APB read data busPCLKDBG
PRDATASYS[31:0]Output

System APB read data bus

APB-Mux

PCLKSYS
PREADYDBGInputDebug APB ready signalPCLKDBG
PREADYSYSOutput

System APB ready signal

APB-Mux

PCLKSYS
PRESETDBGnInputDebug APB resetPCLKDBG
PRESETSYSnInput

System APB reset

APB-Mux

PCLKSYS
PSELDBGOutputDebug APB select. LOW when accessing the DAP ROM APB-MuxPCLKDBG
PSELSYSInput

System APB select

APB-Mux

PCLKSYS
PSLVERRDBGInputDebug APB transfer error signalPCLKDBG
PSLVERRSYSOutput

System APB transfer error signal

APB-Mux

PCLKSYS
PWDATADBG[31:0]Output

Debug APB write data bus

APB-Mux

PCLKDBG
PWDATASYS[31:0]Input

System APB Write data bus

APB-Mux

PCLKSYS
PWRITEDBGOutput

Debug APB write transfer

APB-Mux

PCLKDBG
PWRITESYSInput

System APB write transfer

APB-Mux

PCLKSYS
SEInputScan EnableNone
SPIDENInputEnables secure/privileged debug, TrustZone enable AHB-APNone
SRSTCONNECTED[7:0]Input

JTAG ports support Subsystem Reset, static value

JTAG-AP

PCLKDBG
SWCLKTCKInput

Serial Wire Clock and TAP Clock

SWJ-DP

N/A
SWDITMSInput

Serial Wire Data Input and TAP Test Mode Select

SWJ-DP

SWCLKTCK
SWDOOutput

Serial Wire Data Output

SWJ-DP

SWCLKTCK
SWDOENOutput

Serial Wire Data Output Enable

SWJ-DP

SWCLKTCK
TARGETID[31:0]Input

Uniquely identifies the part, see Target ID

SWJ-DP

SWCLKTCK
TDIInput

TAP Data In

SWJ-DP

SWCLKTCK
TDOOutput

TAP Data Out

SWJ-DP

SWCLKTCK

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