A.3.1. CoreSight CTI signals

Table A.2 shows the CoreSight Cross Trigger Interface (CTI) signals.

Table A.2. CoreSight CTI signals

NameTypeDescriptionClock domain
CIHSBYPASS[3:0]InputChannel interface H/S bypassCTICLK
CISBYPASS InputChannel interface sync bypass CTICLK
CTIAPBSBYPASS InputBetween APB and CTI clock CTICLK
CTICHIN[3:0] InputChannel InCTICLK/None
CTICHOUTACK[3:0] InputChannel Out acknowledgeCTICLK/None
CTICLKInputCTI ClockN/A
CTICLKENInputCTI Clock EnableCTICLK
CTITRIGIN[7:0] InputTrigger InCTICLK/None
CTITRIGOUTACK[7:0]InputTrigger Out acknowledgeCTICLK/None
DBGEN InputInvasive Debug enableNone
nCTIRESETInputResetCTICLK
NIDEN InputNoninvasive debug enableNone
PADDRDBG[11:2] InputDebug APB address busPCLKDBG
PADDRDBG31InputDebug APB programming origin, HIGH for off-chipPCLKDBG
PCLKDBG InputDebug APB clockN/A
PCLKENDBG InputDebug APB clock enablePCLKDBG
PENABLEDBG InputDebug APB enable signal, indicates second and subsequent cyclesPCLKDBG
PRESETDBGn InputDebug APB resetPCLKDBG
PSELDBG InputDebug APB component selectPCLKDBG
PWDATADBG[31:0] InputDebug APB write data busPCLKDBG
PWRITEDBG InputDebug APB write transferPCLKDBG
SEInputScan EnableNone
TIHSBYPASS[7:0]InputTrigger interface H/S bypass, static valueCTICLK
TINIDENSEL[3:0] InputMask when NIDEN is LOW, static valueCTICLK
TISBYPASSACK[7:0] InputTrigger Out ACK Sync bypass, static valueCTICLK
TISBYPASSIN[7:0] InputTrigger In Sync bypass, static valueCTICLK
TODBGENSEL[3:0] InputMask when DBGEN is LOW, static valueCTICLK
ASICCTL[7:0] OutputExternal multiplexor controlCTICLK
CTICHINACK[3:0] OutputChannel In acknowledgeCTICLK
CTICHOUT[3:0]OutputChannel OutCTICLK
CTITRIGINACK[7:0]OutputTrigger In acknowledgeCTICLK
CTITRIGOUT[7:0]OutputTrigger OutCTICLK
PRDATADBG[31:0]OutputDebug APB read data busPCLKDBG
PREADYDBGOutputDebug APB Ready signalPCLKDBG

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