A.7. CoreSight TPIU signals

Table A.7 shows the CoreSight Trace Port Interface Unit (TPIU) signals.

Table A.7. CoreSight TPIU signals

NameTypeDescriptionClock domain
AFREADYS InputATB Data flush complete for the master portATCLK
ATBYTESS[1:0]InputATB Number of valid bytes, LSB aligned, on the slave portATCLK
ATCLK InputATB clockN/A
ATCLKEN InputATB clock enableATCLK
ATDATAS[31:0] InputATB Trace data on the slave portATCLK
ATIDS[6:0] InputATB ID for current trace data on slave portATCLK
ATRESETnInputATB Reset for the ATCLK domainATCLK
ATVALIDS InputATB Valid signals present on slave portATCLK
EXTCTLIN[7:0] InputExternal control inputATCLK
FLUSHIN InputFlush input from the CTIATCLK/None
PADDRDBG[11:0] InputDebug APB address busPCLKDBG
PADDRDBG31 InputDebug APB programming origin, HIGH for off-chipPCLKDBG
PCLKDBG InputDebug APB clockN/A
PCLKENDBG InputDebug APB clock enablePCLKDBG
PENABLEDBG InputDebug APB enable signal, indicates second and subsequent cyclesPCLKDBG
PRESETDBGn InputDebug APB resetPCLKDBG
PSELDBG InputDebug APB component selectPCLKDBG
PWDATADBG[31:0] InputDebug APB write data busPCLKDBG
PWRITEDBG InputDebug APB write transferPCLKDBG
SEInputScan EnableNone
TPCTLInputTie-off to report presence of TRACECTL, static valueATCLK
TPMAXDATASIZE[4:0]InputTie-off to report maximum number of pins on TRACEDATA, static valueATCLK
TRACECLKIN InputTrace clockN/A
TRESETn InputTrace clock resetTRACECLKIN
TRIGIN InputTrigger input from the CTIATCLK/None
AFVALIDS OutputATB Data flush request for the master portATCLK
ATREADYS OutputATB transfer ready on slave portATCLK
EXTCTLOUT[7:0] OutputExternal control outputATCLK
FLUSHINACK OutputFlush input acknowledgementATCLK
PRDATADBG[31:0] OutputDebug APB read data busPCLKDBG
PREADYDBGOutputDebug APB Ready signalPCLKDBG
TRACECLK OutputExported Trace Port Clock, TRACECLKIN divided by 2TRACECLKIN
TRACECTLOutputTrace Port ControlTRACECLKIN
TRACEDATA[31:0] OutputTrace Port DataTRACECLKIN
TRIGINACK OutputTrigger input acknowledgementATCLK

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