A.4. CoreSight replicator signals

Table A.4 shows the CoreSight replicator signals.

Table A.4. CoreSight replicator signals

Name TypeDescriptionClock domain
AFREADYSInputATB Data flush complete for the master portATCLK
AFVALIDM0 InputATB Data flush request for the master port 0ATCLK
AFVALIDM1 InputATB Data flush request for the master port 1ATCLK
ATBYTESS[1:0] InputATB Number of valid bytes, LSB aligned, on the slave portATCLK
ATCLK InputATB clockN/A
ATCLKENInputATB clock enableATCLK
ATDATAS[31:0] InputATB Trace data on the slave portATCLK
ATIDS[6:0] InputATB ID for current trace data on slave portATCLK
ATREADYM0 InputATB transfer ready on master port 0ATCLK
ATREADYM1 InputATB transfer ready on master port 1ATCLK
ATRESETnInputATB Reset for the ATCLK domainATCLK
ATVALIDSInputATB Valid signals present on slave portATCLK
SE InputScan EnableNone
AFREADYM0OutputATB Data flush complete for the master port 0ATCLK
AFREADYM1OutputATB Data flush complete for the master port 1ATCLK
AFVALIDSOutputATB Data flush request for the master portATCLK
ATBYTESM0[1:0] OutputATB Number of valid bytes, LSB aligned, on the master portATCLK
ATBYTESM1[1:0] OutputATB Number of valid bytes, LSB aligned, on the master portATCLK
ATDATAM0[31:0]OutputATB Trace data on the master port 0ATCLK
ATDATAM1[31:0]OutputATB Trace data on the master port 1ATCLK
ATIDM0[6:0] OutputATB ID for current trace data on master port 0ATCLK
ATIDM1[6:0] OutputATB ID for current trace data on master port 1ATCLK
ATREADYSOutputATB transfer ready on slave portATCLK
ATVALIDM0 OutputATB Valid signals present on master port 0ATCLK
ATVALIDM1 OutputATB Valid signals present on master port 1ATCLK

Copyright © 2004-2009 ARM. All rights reserved.ARM DDI 0314H
Non-Confidential