A.6. CoreSight trace funnel signals

Table A.6 shows the CoreSight trace funnel signals.

Table A.6. CoreSight trace funnel signals

NameTypeDescriptionClock domain
AFREADYS0InputATB Data flush complete for the slave port 0ATCLK
AFREADYS1InputATB Data flush complete for the slave port 1ATCLK
AFREADYS2InputATB Data flush complete for the slave port 2ATCLK
AFREADYS3InputATB Data flush complete for the slave port 3ATCLK
AFREADYS4InputATB Data flush complete for the slave port 4ATCLK
AFREADYS5InputATB Data flush complete for the slave port 5ATCLK
AFREADYS6InputATB Data flush complete for the slave port 6ATCLK
AFREADYS7InputATB Data flush complete for the slave port 7ATCLK
AFVALIDM InputATB Data flush request for the master portATCLK
ATBYTESS0[1:0]InputATB Number of valid bytes, LSB aligned, on the slave port 0ATCLK
ATBYTESS1[1:0]InputATB Number of valid bytes, LSB aligned, on the slave port 1ATCLK
ATBYTESS2[1:0]InputATB Number of valid bytes, LSB aligned, on the slave port 2ATCLK
ATBYTESS3[1:0]InputATB Number of valid bytes, LSB aligned, on the slave port 3ATCLK
ATBYTESS4[1:0]InputATB Number of valid bytes, LSB aligned, on the slave port 4ATCLK
ATBYTESS5[1:0]InputATB Number of valid bytes, LSB aligned, on the slave port 5ATCLK
ATBYTESS6[1:0]InputATB Number of valid bytes, LSB aligned, on the slave port 6ATCLK
ATBYTESS7[1:0]InputATB Number of valid bytes, LSB aligned, on the slave port 7ATCLK
ATCLKInputATB clockN/A
ATCLKENInputATB clock enableATCLK
ATDATAS0[31:0] InputATB Trace data on the slave port 0ATCLK
ATDATAS1[31:0] InputATB Trace data on the slave port 1ATCLK
ATDATAS2[31:0] InputATB Trace data on the slave port 2ATCLK
ATDATAS3[31:0] InputATB Trace data on the slave port 3ATCLK
ATDATAS4[31:0] InputATB Trace data on the slave port 4ATCLK
ATDATAS5[31:0] InputATB Trace data on the slave port 5ATCLK
ATDATAS6[31:0] InputATB Trace data on the slave port 6ATCLK
ATDATAS7[31:0] InputATB Trace data on the slave port 7ATCLK
ATIDS0[6:0] InputATB ID for current trace data on slave port 0ATCLK
ATIDS1[6:0] InputATB ID for current trace data on slave port 1ATCLK
ATIDS2[6:0] InputATB ID for current trace data on slave port 2ATCLK
ATIDS3[6:0] InputATB ID for current trace data on slave port 3ATCLK
ATIDS4[6:0] InputATB ID for current trace data on slave port 4ATCLK
ATIDS5[6:0] InputATB ID for current trace data on slave port 5ATCLK
ATIDS6[6:0] InputATB ID for current trace data on slave port 6ATCLK
ATIDS7[6:0] InputATB ID for current trace data on slave port 7ATCLK
ATREADYM InputATB transfer ready on master portATCLK
ATRESETnInputATB Reset for the ATCLK domainATCLK
ATVALIDS0InputATB Valid signals present on slave port 0ATCLK
ATVALIDS1InputATB Valid signals present on slave port 1ATCLK
ATVALIDS2InputATB Valid signals present on slave port 2ATCLK
ATVALIDS3InputATB Valid signals present on slave port 3ATCLK
ATVALIDS4InputATB Valid signals present on slave port 4ATCLK
ATVALIDS5InputATB Valid signals present on slave port 5ATCLK
ATVALIDS6InputATB Valid signals present on slave port 6ATCLK
ATVALIDS7InputATB Valid signals present on slave port 7ATCLK
PADDRDBG[11:2] InputDebug APB address busPCLKDBG
PADDRDBG31 InputDebug APB programming origin, HIGH for off-chipPCLKDBG
PCLKDBG InputDebug APB clockN/A
PCLKENDBGInputDebug APB clock enablePCLKDBG
PENABLEDBG InputDebug APB enable signal, indicates second and subsequent cyclesPCLKDBG
PRESETDBGn InputDebug APB resetPCLKDBG
PSELDBG InputDebug APB component selectPCLKDBG
PWDATADBG[31:0] InputDebug APB write data busPCLKDBG
PWRITEDBG InputDebug APB write transferPCLKDBG
SEInputScan EnableNone
AFREADYM OutputATB Data flush complete for the master portATCLK
AFVALIDS0 OutputATB Data flush request for the slave port 0ATCLK
AFVALIDS1 OutputATB Data flush request for the slave port 1ATCLK
AFVALIDS2 OutputATB Data flush request for the slave port 2ATCLK
AFVALIDS3 OutputATB Data flush request for the slave port 3ATCLK
AFVALIDS4 OutputATB Data flush request for the slave port 4ATCLK
AFVALIDS5 OutputATB Data flush request for the slave port 5ATCLK
AFVALIDS6 OutputATB Data flush request for the slave port 6ATCLK
AFVALIDS7 OutputATB Data flush request for the slave port 7ATCLK
ATBYTESM[1:0]OutputATB Number of valid bytes, LSB aligned, on the master portATCLK
ATDATAM[31:0]OutputATB Trace data on the master portATCLK
ATIDM[6:0] OutputATB ID for current trace data on master portATCLK
ATREADYS0 OutputATB transfer ready on slave port 0ATCLK
ATREADYS1 OutputATB transfer ready on slave port 1ATCLK
ATREADYS2 OutputATB transfer ready on slave port 2ATCLK
ATREADYS3 OutputATB transfer ready on slave port 3ATCLK
ATREADYS4 OutputATB transfer ready on slave port 4ATCLK
ATREADYS5 OutputATB transfer ready on slave port 5ATCLK
ATREADYS6 OutputATB transfer ready on slave port 6ATCLK
ATREADYS7 OutputATB transfer ready on slave port 7ATCLK
ATVALIDM OutputATB Valid signals present on master portATCLK
PRDATADBG[31:0] OutputDebug APB read data busPCLKDBG
PREADYDBG OutputDebug APB Ready signalPCLKDBG

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