A.3.2. CoreSight CTM signals

Table A.3 shows the CoreSight Cross Trigger Matrix (CTM) signals.

Table A.3. CoreSight CTM signals

NameTypeDescriptionClock domain
CIHSBYPASS0[3:0]InputHandshaking bypass port 0CTMCLK
CIHSBYPASS1[3:0]InputHandshaking bypass port 1CTMCLK
CIHSBYPASS2[3:0]InputHandshaking bypass port 2CTMCLK
CIHSBYPASS3[3:0] InputHandshaking bypass port 3CTMCLK
CISBYPASS0InputSync bypass for port 0CTMCLK
CISBYPASS1InputSync bypass for port 1CTMCLK
CISBYPASS2InputSync bypass for port 2CTMCLK
CISBYPASS3InputSync bypass for port 3CTMCLK
CTMCHIN0[3:0]InputChannel In port 0CTMCLK
CTMCHIN1[3:0]InputChannel In port 1CTMCLK/None
CTMCHIN2[3:0]InputChannel In port 2CTMCLK/None
CTMCHIN3[3:0]InputChannel In port 3CTMCLK/None
CTMCHOUTACK0[3:0] InputChannel Out ACK port 0CTMCLK/None
CTMCHOUTACK1[3:0] InputChannel Out ACK port 1CTMCLK/None
CTMCHOUTACK2[3:0] InputChannel Out ACK port 2CTMCLK/None
CTMCHOUTACK3[3:0] InputChannel Out ACK port 3CTMCLK/None
CTMCLKInputClockN/A
CTMCLKENInputClock EnableCTMCLK
nCTMRESET InputResetCTMCLK
SEInputScan EnableNone
CTMCHINACK0[3:0] OutputChannel IN ACK port 0CTMCLK
CTMCHINACK1[3:0] OutputChannel IN ACK port 1CTMCLK
CTMCHINACK2[3:0] OutputChannel IN ACK port 2CTMCLK
CTMCHINACK3[3:0] OutputChannel IN ACK port 3CTMCLK
CTMCHOUT0[3:0]OutputChannel OUT port 0CTMCLK
CTMCHOUT1[3:0]OutputChannel OUT port 1CTMCLK
CTMCHOUT2[3:0]OutputChannel OUT port 2CTMCLK
CTMCHOUT3[3:0]OutputChannel OUT port 3CTMCLK

Copyright © 2004-2009 ARM. All rights reserved.ARM DDI 0314H
Non-Confidential