A.5. CoreSight synchronous bridge signals

Table A.5 shows the CoreSight synchronous bridge signals.

Table A.5. CoreSight synchronous bridge signals

NameTypeDescriptionClock domain
AFREADYSInputATB data flush complete for the master portATCLK
AFVALIDMInputATB data flush request for the master portATCLK
ATBYTESS[1:0]InputATB number of valid bytes, LSB aligned, on the slave portATCLK
ATCLKInputATB clockN/A
ATCLKENInputATB clock enableATCLK
ATDATAS[31:0]InputATB trace data on the slave portATCLK
ATIDS[6:0]InputATB ID for current trace data on slave portATCLK
ATREADYMInputATB transfer ready on master portATCLK
ATRESETnInputATB reset for the ATCLK domainATCLK
ATVALIDSInputATB valid signals present on slave portATCLK
SEInputScan EnableNone
AFREADYMOutputATB data flush complete for the master portATCLK
AFVALIDSOutputATB data flush request for the master portATCLK
ATBYTESM[1:0]OutputATB number of valid bytes, LSB aligned, on the master portATCLK
ATDATAM[31:0]OutputATB trace data on the master portATCLK
ATIDM[6:0]OutputATB ID for current trace data on master portATCLK
ATREADYSOutputATB transfer ready on slave portATCLK
ATVALIDMOutputATB valid signals present on master portATCLK

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