7.5. CoreSight management registers for CSTF

This section gives information specific to the CSTF programmable registers.

Claim tags, 0xFA0 and 0xFA4

The CSTF implements a four-bit claim tag. The use of bits [3:0] is software defined.

Lock access mechanism, 0xFB0 and 0xFB4

The CSTF implements two memory maps controlled through PADDRDBG31. When PADDRDBG31 is HIGH, the Lock Status Register reads as 0x0 indicating that no lock exists. When PADDRDBG31 is LOW, the Lock Status Register reads as 0x3 from reset. This indicates a 32-bit lock access mechanism is present and is locked.

Authentication Status, 0xFB8 [7:0]

Reports the required security level. This is set to 0x00 for functionality not implemented.

Device ID, 0xFC8

The CSTF has the default value of 0x28. Table 7.12 shows the Device ID bit assignments.

Table 7.12. CSTF Device ID bit assignments

[7:4]0x2The CSTF implements a static priority scheme.

This is the value of the Verilog define PORTCOUNT and represents the number of input ports connected. By default all 8 ports are connected. 0x0 and 0x1 are illegal values.

Device Type Identifier, 0xFCC [7:0]

A value of 0x12 identifies this device as a trace link (0x2) and specifically as a funnel/router (0x1).

PartNumber, 0xFE4 [3:0], 0xFE0 [7:4], 0xFE0 [3:0]

Upper, middle, and lower BCD value of Device number. Set to 0x908.

Designer JEP106 value, 0xFD0[3:0], 0xFE8[2:0], 0xFE4[7:4]

The CSTF is identified as an ARM component with a JEP106 identity at 0x3B and a JEP106 continuation code at 0x4 (fifth bank).

Component class, 0xFF4[7:4]

The CSTF complies to the CoreSight class of components and this value is set to 0x9.

See Table 1.1 for the current value of the revision field at offset 0xFE8[7:4].

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