4.6. ECT CoreSight defined registers

See the CoreSight Architecture Specification for the definitions of these registers.

The information given here is specific to the ECT:

Claim tags, 0xFA0 and 0xFA4

The CTI implements a four-bit claim tag. The use of bits [3:0] is software defined.

Lock access mechanism, 0xFB0 and 0xFB4

The CTI implements two memory maps controlled through PADDRDBG31. When PADDRDBG31 is HIGH, the Lock Status Register reads as 0x0 indicating that no lock exists. When PADDRDBG31 is LOW, the Lock Status Register reads as 0x3 from reset. This indicates a 32-bit lock access mechanism is present and is locked.

Authentication Status Register, 0xFB8

Reports the required security level. Table 4.23 shows the authentication values.

Table 4.23. Authentication values for ECT

BitsValueDescription
[31:4]0x0000000Reserved
[3]-

Current value of noninvasive debug enable signals

[2]1'b1Non-invasive debug controlled
[1]-

Current value of invasive debug enable signals

[0]1'b1Invasive debug controlled

Device ID, 0xFC8

The CTI has the default value of 0x40800. Table 4.24 shows the Device ID bit values.

Table 4.24. Device ID bit values

BitsValueDescription
[31:20]0x000Reserved.
[19:16]0x4Number of ECT channels available.
[15:8]0x08Number of ECT triggers available.
[7:5]3'b000Reserved.
[4:0]Implementation defined

Indicates the number of multiplexing available on Trigger Inputs and Trigger Outputs using ASICCTL. Default value of 5'b00000 indicating no multiplexing present. Reflects the value of the Verilog `define EXTMUXNUM that you must alter accordingly.


Device Type Identifier, 0xFCC

0x14 indicates this device has a major type of debug control logic component (0x4) and sub-type corresponding to cross trigger (0x1).

Part number, 0xFE4[3:0], 0xFE0[7:4], and 0xFE0[3:0]

Upper, middle and lower BCD value of Device number. Set to 0x906 for the CTI.

Designer JEP106 value, 0xFD0[3:0], 0xFE8[2:0], 0xFE4[7:4]

The CTI is identified as an ARM component with a JEP106 identity at 0x3B and a JEP106 continuation code at 0x4 (fifth bank).

Component class, 0xFF4[7:4]

The CTI complies to the CoreSight class of components and this value is set to 0x9.

See Table 1.1 for the current value of the revision field at offset 0xFE8[7:4].

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