2.4.3. Transfer timings

This section describes the interaction between the timing of transactions on the serial wire interface, and the DAP internal bus transfers. It shows when the target responds with a WAIT acknowledgement.

Figure 2.8 shows the effect of signalling ACK = WAIT on the length of the packet.

Figure 2.8. SW-DP acknowledgement timing


An access port access results in the generation of a transfer on the DAP internal bus. These transfers have an address phase and a data phase. The data phase can be extended by the access if it requires extra time to process the transaction, for example, if it has to perform an AHB access to the system bus to read data.

Table 2.3 shows the terms used in Figure 2.9 to Figure 2.11.

Table 2.3. Terms used in SW-DP timing

TermDescription
W.APACCWrite a DAP access port register.
R.APACCRead a DAP access port register.
xxPACCRead or write, to debug port or access port register.
WD[0]First write packet data.
WD[-1]Previous write packet data. A transaction that happened before this timeframe.
WD[1]Second write packet data.
RD[0]First read packet data.
RD[1]Second read packet data.

Figure 2.9 shows a sequence of write transfers. It shows that a single new transfer, WD[1], can be accepted by the serial engine, while a previous write transfer, WD[0], is completing. Any subsequent transfer must be stalled until the first transfer completes.

Figure 2.9. SW-DP to DAP bus timing for write


Figure 2.10 shows a sequence of read transfers. It shows that the payload for an access port read transfer provides the data for the previous read request. A read transfer only stalls if the previous transfer has not completed, therefore the first read transfer returns undefined data. It is still necessary to return data to ensure that the protocol timing remains predictable.

Figure 2.10. SW-DP to DAP bus timing for read


Figure 2.11 shows a sequence of transfers separated by IDLE periods. It shows that the wire is always handed back to the host after any transfer.

Figure 2.11. SW-DP idle timing


After the last bit in a packet, the line can be LOW, or Idle, for any period longer than a single bit, to enable the Start bit to be detected for back-to-back transactions.

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