2.11.5. APB-Mux clocks, power, and resets

The APB-Mux has two clocks:

PCLKDBG

Drives all logic, except for the System Slave port interface.

PCLKSYS

Drives the System Slave port interface.

The APB-Mux has an asynchronous interface between the System Slave port and the rest of the APB-Mux, as shown in Figure 2.32. The asynchronous interface defines a common boundary between:

Figure 2.32. APB-Mux domains


Effects of power down

The debug and system power domains can be independently powered up and down. Accesses from tools to the debug APB through the APB-Mux can only be performed when the Debug APB is powered up, therefore this access mechanism does not cross asynchronous domains. PSLVERRAP is only returned HIGH if a Debug APB component has driven this signal HIGH. A system access to the Debug APB, when the Debug APB is powered down, must return PSLVERRSYS HIGH to indicate that a transaction is unsuccessful. nCDBGPWRDN enables the APB Mux to detect if the debug domain is powered down.

Effects of resets

The debug and system domains can be independently reset. A reset initiated from either domain must not cause a protocol violation in the other domain.

  • If the Debug APB is reset during a system level write access to the debug infrastructure, the System Slave port must return PSLVERRSYS HIGH. The write operation is not performed.

  • If the Debug APB is reset during a system level read access to the debug infrastructure, the System Slave port must return PSLVERRSYS HIGH. The read data is undefined.

  • If the System APB is reset during a Debug APB access from the APB-AP, this must not invalidate the existing transfer already in progress from the APB-AP Slave port on the APB-Mux.

  • If the System APB is reset during a system level access to the debug infrastructure then the APB-Mux must hold the existing transfer values to complete the Debug APB transaction without violating the APB protocol. A system write transfer to Debug APB, if already initiated, must complete. A system read transfer to Debug APB, if already initiated, must complete up to the APB-Mux master interface.

Output clamping

If the APB-Mux is split across multiple power domains, with the PCLKDBG driven side in the Debug domain, and the system slave port in the SoC power domain, clamping logic must be instantiated on the outputs of signals crossing each power down domain.

Figure 2.33 shows the RTL structure to support power domain separation.

Figure 2.33. APB-Mux power domain separation


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