8.7.1. Programming registers

There are two registers that contain information relating to the physical Trace Out port. These are the Supported Port Size Register and the Formatter and Flush Status Register. For more information about these registers see Supported Port Size Register, 0x000 and Formatter and Flush Control Register, 0x304.

Constraining the supported TRACEDATA port widths

The TPIU currently supports data port widths from 1-32 bits. A Verilog `define, CSTPIU_SUPPORTSIZE_VAL, is used to state the supported port sizes by the RTL. This is currently set to report that all options are supported and is not user modifiable.

When placing on an Application Specific Integrated Circuit (ASIC), not all the signals of TRACEDATA can go to pads, that is, only TRACEDATA[(MDS-1):0] go to pins, where MDS represents the Maximum Data Size going to pins. If MDS is not 32, that is, the maximum supported data width for capture by a TPA is less than 32 bits of data, this must be reflected in the programmers view of the Supported Port Size Register through the tie-off input TPMAXDATASIZE[4:0]. See Supported Port Size Register, 0x000 for more details.

The tie-off must be set to represent the number of TRACEDATA connections that go to ASIC pads, with all LOW indicating 1 pin, which is the minimum possible, and all HIGH indicating 32 pins, which is a full TRACEDATA bus. For example, if a 16-bit trace port is implemented, that is TRACEDATA[15:0] is connected, then TPMAXDATASIZE[4:0] must be tied to 0x0F. With a maximum TRACEDATA[7:0] connected to the ASIC, the tie-offs must be set to 0x07.

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