8.11.2. Supported options

Patterns operate over all the TRACEDATA pins for a given port width setting. Test patterns are aware of port sizes and always align to TRACEDATA[0]. Walking bit patterns wrap at the highest data pin for the selected port width even if the device has a larger port width available. Also, the alternating patterns do not affect unenabled data pins on smaller trace port sizes.

Walking 1s

All output pins clear (0) with a single bit set at a time, tracking across every TRACEDATA output pin. This can be used to watch for data edge timing, or synchronization, high voltage level of logic 1 and cross talk against adjacent wires. This can also be used as a simple way to test for broken/faulty cables and data signals.

Walking 0s

All output pins are set (1) with a single bit cleared at a time, tracking across every TRACEDATA output pin. In a similar way to the walking 1s this can be used to watch for data edge timing, or synchronization, low voltage level of logic 0, cross talk, and ground lift.

Alternating AA/55 pattern

Alternate TRACEDATA pins set with the others clear. This alternates every cycle with the sequence starting with TRACEDATA[1] set ('AA' pattern == 8'b1010_1010) and then TRACEDATA[0] set ('55' pattern == 8'b0101_0101). The pattern repeats over the entire selected bus width. This pattern can be used to check voltage levels, cross talk and data edge timing.

Alternating FF/00 pattern

On each clock cycle the TRACEDATA pins are either all set ('FF' pattern) or all cleared ('00' pattern). This sequence of alternating the entire set of data pins is a good way to check any power supply stability to the TPIU and the final pads because of the stresses the drivers are under.

Combinations of patterns

Each selected pattern is repeated for a defined number of cycles before moving onto the next pattern. After all patterns have been performed, the unit switches to normal mode that is, tracing data. If some combination is chosen and the continuous mode selected, each pattern runs for the number of cycles indicated in the repeat counter register before looping around enabled parameters.

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