9.1.4. Memory BIST interface

Table 9.3 shows the Memory BIST interface ports.

Table 9.3. ETB Memory BIST interface ports

NameTypeDescription
MBISTADDR [CSETB_ADDR_WIDTH-1:0]Input

Address bus for the external BIST controller, active when MTESTON is HIGH.

CSETB_ADDR_WIDTH defines the address bus width used, and therefore the RAM depth supported.

MBISTCEInputActive HIGH chip select for external BIST controller, active when MTESTON is HIGH.
MBISTDIN[31:0]InputWrite data bus for external BIST controller, active when MTESTON is HIGH.
MBISTDOUT[31:0]OutputRead data bus for external BIST controller, active when MTESTON is HIGH.
MBISTWEInputActive HIGH write enable for external BIST controller, active when MTESTON is HIGH.
MTESTONInputEnable signal for the external BIST controller.

Copyright © 2004-2009 ARM. All rights reserved.ARM DDI 0314H
Non-Confidential