CoreSight™ Components Technical Reference Manual


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Conventions
Further reading
Feedback
Feedback on this product
Feedback on content
1. Introduction
1.1. About the CoreSight components
1.1.1. Capabilities
1.1.2. Structure of the CoreSight Design Kit
1.2. CoreSight block summary
1.3. Typical CoreSight Design Kit debugging environment
2. Debug Access Port
2.1. About the Debug Access Port
2.1.1. DAP flow of control
2.2. SWJ-DP
2.2.1. Structure of the SWJ-DP
2.2.2. Operation of the SWJ-DP
2.2.3. JTAG and SWD interface
2.2.4. Clock, reset and power domain support
2.2.5. SWD and JTAG selection mechanism
2.3. JTAG-DP
2.3.1. Overview
2.3.2. Implementation specific details
2.4. SW-DP
2.4.1. Overview
2.4.2. Implementation specific details
2.4.3. Transfer timings
2.4.4. SW-DP multi-drop support
2.5. Common debug port features and registers
2.5.1. Features overview
2.5.2. Example pushed operations
2.5.3. Debug Port registers overview
2.5.4. Implementation specific registers
2.6. Access ports
2.6.1. Overview
2.7. AHB-AP
2.7.1. External interfaces
2.7.2. Implementation features
2.7.3. Programmers model overview
2.7.4. DAP transfers
2.7.5. Differentiation between system and access port initiated error responses
2.7.6. Effects of resets
2.7.7. Effects of power down signals
2.7.8. AHB-AP dual power domain support
2.8. APB-AP
2.8.1. External interfaces
2.8.2. Implementation features
2.8.3. Programmers model overview
2.8.4. APB-AP Control/Status Word Register, CSW, 0x00
2.8.5. APB-AP Transfer Address Register, TAR, 0x04
2.8.6. APB-AP Data Read/Write Register, DRW, 0x0C
2.8.7. APB-AP Banked Data Registers, BD0-BD3, 0x10-0x1C
2.8.8. Debug APB ROM Address, ROM, 0xF8
2.8.9. APB-AP Identification Register
2.8.10. DAP transfers
2.9. JTAG-AP
2.9.1. External interfaces
2.9.2. RTCK connections
2.9.3. Programmers model overview
2.10. Auxiliary Access Port
2.11. APB multiplexor
2.11.1. APB-Mux port definitions
2.11.2. APB-Mux miscellaneous signals
2.11.3. APB-Mux arbitration and APB Mux connectivity
2.11.4. APB-Mux Software Access Enable
2.11.5. APB-Mux clocks, power, and resets
2.12. ROM table
2.12.1. ROM table registers
2.12.2. ROM table entries
2.13. Authentication requirements for Debug Access Port
2.14. Clocks, power, and resets
3. CoreSight Trace Sources
3.1. AMBA AHB Trace Macrocell
3.1.1. Ports
3.1.2. Authentication requirements for the HTM
3.2. Embedded Trace Macrocells
3.2.1. Ports
4. Embedded Cross Trigger
4.1. About the Embedded Cross Trigger
4.1.1. How ECT works
4.1.2. CTI handshaking, synchronization, and clocks
4.2. ECT programmers model
4.3. Summary of CTI registers
4.4. CTI register descriptions
4.4.1. CTI Control Register, CTICONTROL, 0x000
4.4.2. CTI Interrupt Acknowledge Register, CTIINTACK, 0x010
4.4.3. CTI Application Trigger Set Register, CTIAPPSET, 0x014
4.4.4. CTI Application Trigger Clear Register, CTIAPPCLEAR, 0x018
4.4.5. CTI Application Pulse Register, CTIAPPPULSE, 0x01C
4.4.6. CTI Trigger to Channel Enable Registers, CTIINEN0-7, 0x020-0x03C
4.4.7. CTI Channel to Trigger Enable Registers, CTIOUTEN0-7, 0x0A0-0x0BC
4.4.8. CTI Trigger In Status Register, CTITRIGINSTATUS, 0x130
4.4.9. CTI Trigger Out Status Register, CTITRIGOUTSTATUS, 0x134
4.4.10. CTI Channel In Status Register, CTICHINSTATUS, 0x138
4.4.11. CTI Channel Out Status Register, CTICHOUTSTATUS, 0x13C
4.4.12. Enable CTI Channel Gate Register, CTIGATE, 0x140
4.4.13. External Multiplexor Control Register, ASICCTL, 0x144
4.5. ECT Integration Test Registers
4.5.1. ITCHINACK Register, 0xEDC
4.5.2. ITTRIGINACK Register, 0xEE0
4.5.3. ITCHOUT Register, 0xEE4
4.5.4. ITTRIGOUT Register, 0xEE8
4.5.5. ITCHOUTACK Register, 0xEEC
4.5.6. ITTRIGOUTACK Register, 0xEF0
4.5.7. ITCHIN Register, 0xEF4
4.5.8. ITTRIGIN Register, 0xEF8
4.6. ECT CoreSight defined registers
4.7. ECT connectivity recommendations
4.7.1. Connections for ARM7 and ARM9 systems
4.7.2. Connections for ARM11 systems
4.7.3. Connections for CoreSight components
4.8. ECT authentication requirements
4.8.1. Trigger inputs
4.8.2. Trigger outputs
4.8.3. ECT authentication signals
5. ATB 1:1 Bridge
5.1. About the ATB 1:1 bridge
5.1.1. Normal operation
5.1.2. Flushing operation
5.1.3. Flushing and data packets
5.2. Authentication requirements for ATB 1:1 Bridge
6. ATB Replicator
6.1. About the ATB replicator
6.1.1. Incoming ATB interface
6.1.2. Outgoing ATB interfaces
6.2. ATB replicator connection behavior
6.2.1. ATREADYS and ATVALIDM
6.2.2. Flushing AFVALIDM and AFREADYM
6.3. Authentication requirements for replicators
7. CoreSight Trace Funnel
7.1. About the CoreSight Trace Funnel
7.1.1. CSTF blocks
7.1.2. Debug APB interface
7.2. CSTF programmers model
7.3. CSTF specific registers
7.3.1. CSTF Control Register, 0x000
7.3.2. CSTF Priority Control Register, 0x004
7.4. CSTF Integration Test Registers
7.4.1. CSTF Integration Test Registers
7.5. CoreSight management registers for CSTF
7.6. Unconnected slave interfaces
7.7. Disabled slave interfaces
7.8. CSTF input arbitration
7.8.1. Static priority
7.8.2. Minimum hold time
7.8.3. Initial register programming
7.8.4. Operation example
7.8.5. Flushing
7.8.6. Flushing example
7.9. Authentication requirements for funnels
8. Trace Port Interface Unit
8.1. About the Trace Port Interface Unit
8.1.1. ATB interface
8.1.2. APB interface
8.2. Trace Out Port
8.3. Miscellaneous connections
8.4. TPIU programmers model
8.5. TPIU CoreSight management registers
8.6. Trace port control registers
8.6.1. Supported Port Size Register, 0x000
8.6.2. Current Port Size Register, 0x004
8.6.3. Supported Trigger Modes Register, 0x100
8.6.4. Trigger Counter Register, 0x104
8.6.5. Trigger Multiplier Register, 0x108
8.6.6. Supported Test Patterns/Modes Register, 0x200
8.6.7. Current Test Patterns/Modes Register, 0x204
8.6.8. TPIU Test Pattern Repeat Counter Register, 0x208
8.6.9. Formatter and Flush Status Register, 0x300
8.6.10. Formatter and Flush Control Register, 0x304
8.6.11. Formatter Synchronization Counter Register, 0x308
8.6.12. TPIU Integration Test Registers
8.6.13. TPIU EXCTL Port Registers
8.7. TPIU trace port sizes
8.7.1. Programming registers
8.7.2. Omission of TRACECTL
8.8. TPIU triggers
8.8.1. Correlation with AFVALID
8.9. Other TPIU design considerations
8.9.1. TRACECLK generation
8.9.2. TRACECTL removal
8.9.3. TRACECTL and TRACEDATA multiplexing
8.9.4. Off-chip based TRACECLKIN
8.10. Authentication requirements for TPIUs
8.11. TPIU pattern generator
8.11.1. Pattern generator modes of operation
8.11.2. Supported options
8.12. TPIU formatter and FIFO
8.12.1. Operational description
8.12.2. Special trace source IDs
8.12.3. Supported modes of operation
8.12.4. Periodic synchronization
8.13. Configuration options
8.13.1. Configuration guidelines
8.14. Example configuration scenarios
8.14.1. Capturing trace after an event and stopping
8.14.2. Only indicating triggers and still flushing
8.14.3. Multiple trigger indications
8.14.4. Independent triggering and flushing
9. Embedded Trace Buffer
9.1. About the ETB for CoreSight
9.1.1. ATB interface
9.1.2. ETB triggering and flushing ports
9.1.3. ETB status ports
9.1.4. Memory BIST interface
9.2. ETB programmers model
9.3. ETB register descriptions
9.3.1. ETB RAM Depth Register, RDP, 0x004
9.3.2. ETB Status Register, STS, 0x00C
9.3.3. ETB RAM Read Data Register, RRD, 0x010
9.3.4. ETB RAM Read Pointer Register, RRP, 0x014
9.3.5. ETB RAM Write Pointer Register, RWP, 0x018
9.3.6. ETB Trigger Counter Register, TRG, 0x01C
9.3.7. ETB Control Register, CTL, 0x020
9.3.8. ETB RAM Write Data Register, RWD, 0x024
9.3.9. ETB Formatter and Flush Status Register, FFSR, 0x300
9.3.10. ETB Formatter and Flush Control Register, FFCR, 0x304
9.3.11. ETB Integration Test Registers
9.4. ETB CoreSight management registers
9.5. ETB clocks, resets, and synchronization
9.5.1. ETB clock domains
9.5.2. ETB resets
9.5.3. ETB synchronization
9.6. ETB Trace capture and formatting
9.6.1. Formatter data processing
9.6.2. Special Trace Source IDs
9.6.3. Special modes of operation
9.6.4. Stopping tracing
9.7. Flush assertion
9.8. Triggers
9.9. Write address generation for trace data storage
9.10. Trace data storage
9.11. APB configuration and RAM access
9.11.1. Read access
9.11.2. Write access
9.12. Trace RAM
9.13. Authentication requirements for CoreSight ETBs
9.14. ETB RAM support
9.14.1. Access sizes
9.14.2. BIST interface
9.14.3. RAM instantiation
9.15. ETB configuration options
9.15.1. ETM architecture version no longer required
9.15.2. RAM options
9.16. Comparisons with ETB11
10. Serial Wire Viewer
10.1. About the Serial Wire Viewer
10.2. SWV interfaces
10.2.1. Clocks and resets
10.2.2. Trace interface ports
10.2.3. APB interface
10.2.4. Miscellaneous ports
10.3. Authentication requirements
10.3.1. Authentication interface signals
11. Serial Wire Output
11.1. About the Serial Wire Output
11.2. SWO ports
11.2.1. ATB interface
11.2.2. APB interface
11.2.3. Trace out ports
11.3. SWO programmers model
11.4. CoreSight defined registers
11.4.1. Integration Mode Control Register, 0xF00 [0]
11.4.2. Claim Tag Set and Clear Registers, 0xFA0 [3:0] and 0xFA4 [3:0]
11.4.3. Lock Access Register, 0xFB0 [31:0]
11.4.4. Lock Status Register, 0xFB4 [2:0]
11.4.5. SWO identification registers
11.5. Trace port control registers
11.5.1. Supported Synchronous Port Size Register, SPR, 0x000
11.5.2. Current Synchronous Port Size Register, CPR, 0x004
11.5.3. Current Output Divisor Register, CODR, 0x010
11.5.4. Selected Pin Protocol Register, SPPR, 0xF0
11.6. Trigger registers
11.6.1. Supported Trigger Mode Register, STMR, 0x100
11.7. EXTCTL registers
11.8. Test pattern registers
11.8.1. Supported Test Patterns and Modes Register, STPR, 0x200
11.9. Formatter and flush registers
11.9.1. Formatter and Flush Status Register, FFSR, 0x300
11.9.2. Formatter and Flush Control Register, FFCR, 0x304
11.10. Integration test registers
11.10.1. Integration Test ATB Data Register 0, ITATBDATA0, 0xEEC
11.10.2. Integration Test ATB Control Register 2, ITATBCTR2, 0xEF0
11.10.3. Integration Test ATB Control Register 0, ITATBCTR0, 0xEF8
11.11. SWO trace port
11.11.1. Supported port sizes
11.11.2. Physical pin protocol
12. Instrumentation Trace Macrocell
12.1. About the Instrumentation Trace Macrocell
12.1.1. Trace packet format
12.1.2. Timestamp packet
12.1.3. Multiple source arbitration
12.1.4. ITM FIFO
12.2. ITM ports
12.2.1. Clocks and resets
12.2.2. APB interface
12.2.3. ATB interface
12.2.4. Miscellaneous ports
12.3. ITM programmers model
12.4. CoreSight defined registers
12.4.1. Integration Mode Control Register, 0xF00
12.4.2. Claim Tag Set Register, 0xFA0, and Claim Tag Clear Register, 0xFA4
12.4.3. Lock Access Register, 0xFB0, and Lock Status Register, 0xFB4
12.4.4. Authentication Status Register, 0xFB8
12.4.5. Device Configuration Register, 0xFC8
12.4.6. Device Type Identifier Register, 0xFCC
12.4.7. Peripheral ID Registers, 0xFDC-0xFE0
12.4.8. Component ID Registers (0xFFC to 0xFF0)
12.5. Stimulus registers
12.6. Trace registers
12.6.1. Trace Enable Register, TER, 0xE00
12.6.2. Trace Trigger Register, TTR, 0xE20
12.7. Control registers
12.7.1. Control Register, CR, 0xE80
12.7.2. Synchronization Control Register, SCR, 0xE90
12.8. Integration test registers
12.8.1. Integration Test Trigger Out Acknowledge Register, ITTRIGOUTACK, 0xEE4
12.8.2. Integration Test Trigger Out Register, ITTRIGOUT, 0xEE8
12.8.3. Integration Test ATB Data Register 0, ITATBDATA0, 0xEEC
12.8.4. Integration Test ATB Control Register 2, ITATBCTR2, 0xEF0
12.8.5. Integration Test ATB Control Register 1, ITATBCTR1, 0xEF4
12.8.6. Integration Test ATB Control Register 0, ITATBCTR0, 0xEF8
12.9. Authentication requirements
12.9.1. Authentication interface signals
A. CoreSight Port List
A.1. Clock domains
A.2. CoreSight DAP signals
A.3. CoreSight ECT signals
A.3.1. CoreSight CTI signals
A.3.2. CoreSight CTM signals
A.4. CoreSight replicator signals
A.5. CoreSight synchronous bridge signals
A.6. CoreSight trace funnel signals
A.7. CoreSight TPIU signals
A.8. CoreSight ETB signals
A.9. CoreSight SWO signals
A.10. CoreSight ITM signals
B. CoreSight Components and Clock Domains
B.1. CoreSight components and clock domains
C. Serial Wire Debug and JTAG Trace Connector
C.1. About the SWD and JTAG trace connector
C.2. Pinout details
C.2.1. Combined pin names
C.2.2. 10-way connector pinouts
C.2.3. 20-way connector pinouts including trace
C.3. Signal definitions
D. Deprecated SWJ-DP Switching Sequences
D.1. About the deprecated SWJ-DP switching sequences
E. Revisions
Glossary

List of Figures

1. Key to timing diagram conventions
1.1. CoreSight debugging environment
2.1. Structure of the CoreSight DAP components
2.2. SWJ Debug Port
2.3. AHB Access Port
2.4. APB Access Port
2.5. DAP flow of control
2.6. SWJ-DP external connections
2.7. SWJ-DP signal clamping
2.8. SW-DP acknowledgement timing
2.9. SW-DP to DAP bus timing for write
2.10. SW-DP to DAP bus timing for read
2.11. SW-DP idle timing
2.12. AP Abort Register bit assignments
2.13. Identification Code Register bit assignments
2.14. Control/Status Register bit assignments
2.15. AP Select Register bit assignments
2.16. Wire Control Register bit assignments
2.17. Target Identification Register bit assignments
2.18. Data Link Protocol Identification Register bit assignments
2.19. AHB-AP Control/Status Word Register bit assignments
2.20. AHB-AP Identification Register bit assignments
2.21. AHB-AP signal clamping
2.22. APB-AP Control/Status Word Register bit assignments
2.23. APB-AP Transfer Address Register bit assignments
2.24. Debug APB ROM Address Register bit assignments
2.25. APB-AP Identification Register bit assignments
2.26. JTAG-AP Control/Status Word Register bit assignments
2.27. JTAG-AP Port Select Register bit assignments
2.28. JTAG-AP Port Status Register bit assignments
2.29. JTAG-AP Identification Register bit assignments
2.30. APB-Mux block diagram
2.31. APB-Mux integrated into the DAP
2.32. APB-Mux domains
2.33. APB-Mux power domain separation
3.1. HTM in a multi-layer bus configuration
4.1. CoreSight CTI and CTM block diagram
4.2. Standard synchronization
4.3. CTI Control Register bit assignments
4.4. CTI Interrupt Acknowledge Register bit assignments
4.5. CTI Application Trigger Set Register bit assignments
4.6. CTI Application Trigger Clear Register bit assignments
4.7. CTI Application Pulse Register bit assignments
4.8. CTI Trigger to Channel Enable Registers bit assignments
4.9. CTI Channel to Trigger Enable Registers bit assignments
4.10. CTI Trigger In Status Register bit assignments
4.11. CTI Trigger Out Status Register bit assignments
4.12. CTI Channel In Status Register bit assignments
4.13. CTI Channel Out Status Register bit assignments
4.14. CTI Channel Gate Register bit assignments
4.15. Channel gate used with the CTI
4.16. External Multiplexor Control Register bit assignments
4.17. ITCINACK Register bit assignments
4.18. ITTRIGINACK Register bit assignments
4.19. ITCHOUT Register bit assignments
4.20. ITTRIGOUT Register bit assignments
4.21. ITCHOUTACK Register bit assignments
4.22. ITTRIGOUTACK Register bit assignments
4.23. ITCHIN Register bit assignments
4.24. ITTRIGIN Register bit assignments
5.1. ATB basic operation
5.2. ATB flushing operation on master and slave interfaces
5.3. ATB flushing data packets
6.1. Example ATB replicator
6.2. ATB replicator flushing behavior
7.1. CSTF block diagram
7.2. CSTF Control Register bit assignments
7.3. CSTF Priority Control Register bit assignments
7.4. Integration Test ATB Data 0 Register bit assignments
7.5. Integration Test ATB Control 2 Register bit assignments
7.6. Integration Test ATB Control 1 Register bit assignments
7.7. Integration Test ATB Control 0 Register bit assignments
7.8. Funnel minimum hold time, two cycles
7.9. Minimum hold time, two cycles with wait
7.10. Example operation with four trace sources
7.11. Flushing operation with four trace sources
8.1. TPIU block diagram
8.2. Supported Port Size Register bit assignments
8.3. Supported Trigger Modes Register bit assignments
8.4. Trigger Counter Register bit assignments
8.5. Trigger Multiplier Register bit assignments
8.6. Supported Test Patterns/Modes Register bit assignments
8.7. Test Pattern Repeat Counter Register bit assignments
8.8. Formatter and Flush Status Register bit assignments
8.9. Formatter and Flush Control Register bit assignments
8.10. Formatter Synchronization Counter Register bit assignments
8.11. Integration Test Trigger In and Flush In Acknowledge Register bit assignments
8.12. Integration Test Trigger In and Flush In Register bit assignments
8.13. Integration Test ATB Data Register 0 bit assignments
8.14. Integration Test ATB Control Register 2 bit assignments
8.15. Integration Test ATB Control Register 1 bit assignments
8.16. Integration Test ATB Control Register 0 bit assignments
8.17. Paths of TRACECLK, TRACEDATA, and TRACECTL to pads
8.18. TRACECLK timing in relation to TRACEDATA and TRACECTL
8.19. Externally derived TRACECLK
8.20. Construction of formatter data packets
8.21. Capturing trace after an event and stopping
8.22. Multiple trigger indications from flushes
8.23. Independent triggering during repeated flushes
9.1. ETB block diagram
9.2. ETB Status Register bit assignments
9.3. ETB Control Register bit assignments
9.4. ETB Formatter and Flush Status Register bit assignments
9.5. ETB Formatter and Flush Control Register bit assignments
9.6. Integration Test Miscellaneous Output Register 0 bit assignments
9.7. Integration Test Trigger In and Flush In Acknowledge Register bit assignments
9.8. Integration Test Trigger In and Flush In Register bit assignments
9.9. Integration Test ATB Data Register 0 bit assignments
9.10. Integration Test ATB Control Register 2 bit assignments
9.11. Integration Test ATB Control Register 1 bit assignments
9.12. Integration Test ATB Control Register 0 bit assignments
9.13. Construction of data packets within the formatter
9.14. Conditions for stopping trace capture
9.15. Generation of flush on FLUSHIN
9.16. Generation of flush from a trigger event
9.17. Generation of a flush on manual
9.18. Generation of a trigger request with continuous formatting enabled
9.19. ETB trace RAM block wrapper
10.1. ITM and SWO as part of a SWV system
11.1. SWO block diagram
11.2. Current Output Divisor Register bit assignments
11.3. Selected Pin Protocol Register bit assignments
11.4. Formatter and Flush Status Register bit assignments
11.5. Formatter and Flush Control Register bit assignments
11.6. Integration Test ATB Data Register 0 bit assignments
11.7. Integration Test ATB Control Register 2 bit assignments
11.8. Integration Test ATB Control Register 0 bit assignments
11.9. SWO Manchester encoded data sequence
11.10. Manchester encoding example
11.11. UART encoded data sequence
12.1. ITM block diagram
12.2. Synchronization packet layout
12.3. Overflow packet layout
12.4. Timestamp packet layout
12.5. SWIT packet layout
12.6. TRIGOUT and TRIGOUTACK operation
12.7. Control Register bit assignments
12.8. Synchronization Control Register bit assignments
12.9. Integration Test Trigger Out Acknowledge Register bit assignments
12.10. Integration Test Trigger Out Register bit assignments
12.11. Integration Test ATB Data Register 0 bit assignments
12.12. Integration Test ATB Control Register 2 bit assignments
12.13. Integration Test ATB Control Register 1 bit assignments
12.14. Integration Test ATB Control Register 0 bit assignments

List of Tables

1.1. CoreSight block summary
2.1. JTAG-DP physical interface
2.2. JTAG-DP registers
2.3. Terms used in SW-DP timing
2.4. TARGETID input connections
2.5. TARGETID mapping
2.6. Summary of Debug Port registers
2.7. AP Abort Register bit assignments
2.8. Identification Code Register bit assignments
2.9. JEDEC JEP-106 manufacturer ID code, with ARM values
2.10. Control/Status Register bit assignments
2.11. AP Select Register bit assignments
2.12. Wire Control Register bit assignments
2.13. Turnaround tristate period field bit definitions
2.14. Wire operating mode bit definitions
2.15. Target Identification Register bit assignments
2.16. Data Link Protocol Identification Register bit assignments
2.17. Other AHB-AP ports
2.18. Example generation of byte lane strobes
2.19. AHB access port registers
2.20. AHB-AP Control/Status Word Register bit assignments
2.21. AHB-AP Transfer Address Register bit assignments
2.22. AHB-AP Data Read/Write Register bit assignments
2.23. Banked Data Register bit assignments
2.24. ROM Address Register bit assignments
2.25. AHB-AP Identification Register bit assignments
2.26. Error responses with DAPSLVERR HIGH and TrInProg LOW
2.27. APB-AP other ports
2.28. APB-AP registers
2.29. APB Control/Status Word Register bit assignments
2.30. APB-AP Transfer Address Register bit assignments
2.31. ABP-AP Data Read/Write Register bit assignments
2.32. APB-AP Banked Data Registers bit assignments
2.33. Debug APB ROM Address Register bit assignments
2.34. APB-AP Identification Register bit assignments
2.35. JTAG to slave device signals
2.36. JTAG-AP register summary
2.37. JTAG-AP Control/Status Word Register bit assignments
2.38. JTAG-AP Port Select Register bit assignments
2.39. JTAG-AP Port Status Register bit assignments
2.40. JTAG-AP Identification Register bit assignments
2.41. APB-Mux miscellaneous signals
2.42. ROM table registers
2.43. ROM table entries bit assignments
4.1. CTI register summary
4.2. CTI Control Register bit assignments
4.3. CTI Interrupt Acknowledge Register bit assignments
4.4. CTI Application Trigger Set Register bit assignments
4.5. CTI Application Trigger Clear Register bit assignments
4.6. CTI Application Pulse Register bit assignments
4.7. CTI Trigger to Channel Enable Registers bit assignments
4.8. CTI Channel to Trigger Enable Registers bit assignments
4.9. CTI Trigger In Status Register bit assignments
4.10. CTI Trigger Out Status Register bit assignments
4.11. CTI Channel In Status Register bit assignments
4.12. CTI Channel Out Status Register bit assignments
4.13. CTI Channel Gate Register bit assignments
4.14. External Multiplexor Control Register bit assignments
4.15. ITCHINACK Register bit assignments
4.16. ITTRIGINACK Register bit assignments
4.17. ITCHOUT Register bit assignments
4.18. ITTRIGOUT Register bit assignments
4.19. ITCHOUTACK Register bit assignments
4.20. ITTRIGOUTACK Register bit assignments
4.21. ITCHIN Register bit assignments
4.22. ITTRIGIN Register bit assignments
4.23. Authentication values for ECT
4.24. Device ID bit values
4.25. Trigger input connections for ARM7 and ARM9 systems
4.26. Trigger output connections for ARM7 and ARM9 systems
4.27. Recommended input connections for use with ARM11 systems
4.28. Recommended output connections for use with ARM11 systems
4.29. Trigger inputs to the CTI
4.30. Trigger outputs from CTI
4.31. ECT recommended trigger outputs
4.32. ECT authentication signals
7.1. CSTF visible registers
7.2. CSTF Control Register bit assignments
7.3. CSTF Priority Control Register bit assignments
7.4. Integration Test ATB Data 0 Register bit assignments on reads
7.5. Integration Test ATB Data 0 Register bit assignments on writes
7.6. Integration Test ATB Control 2 Register bit assignments on reads
7.7. Integration Test ATB Control 2 Register bit assignments on writes
7.8. Integration Test ATB Control 1 Register bit assignments on reads
7.9. Integration Test ATB Control 1 Register bit assignments on writes
7.10. Integration Test ATB Control 1 Register bit assignments on reads
7.11. Integration Test ATB Control 0 Register bit assignments on writes
7.12. CSTF Device ID bit assignments
7.13. Tie-offs for unconnected ports
8.1. Trace Out Port signals
8.2. TPIU miscellaneous ports
8.3. TPIU programmable registers
8.4. Device ID bit values
8.5. Supported Trigger Modes Register bit assignments
8.6. Trigger Counter Register bit assignments
8.7. Supported Trigger Multiplier Register bit assignments
8.8. Supported Test Patterns/Modes Register bit assignments
8.9. Test Pattern Repeat Counter Register bit assignments
8.10. Formatter and Flush Status Register bit assignments
8.11. Formatter and Flush Control Register bit assignments
8.12. Formatter Synchronization Counter Register bit assignments
8.13. Integration Test Trigger In and Flush In Acknowledge Register bit assignments
8.14. Integration Test Trigger In and Flush In Register bit assignments
8.15. Integration Test ATB Data Register 0 bit assignments
8.16. Integration Test ATB Control Register 2 bit assignments
8.17. Integration Test ATB Control Register 1 bit assignments
8.18. Integration Test ATB Control Register 0 bit assignments
8.19. Example Trace Out Port sizes
8.20. CoreSight representation of triggers
9.1. ETB triggering and flushing ports
9.2. ETB status ports
9.3. ETB Memory BIST interface ports
9.4. ETB register summary
9.5. ETB RAM Depth Register bit assignments
9.6. ETB Status Register bit assignments.
9.7. ETB RAM Read Data Register bit assignments.
9.8. ETB RAM Read Pointer Register bit assignments.
9.9. ETB RAM Write Pointer Register bit assignments.
9.10. ETB Trigger Counter Register bit assignments.
9.11. ETB Control Register bit assignments.
9.12. ETB RAM Write Data Register bit assignments
9.13. ETB Formatter and Flush Status Register bit assignments
9.14. ETB Formatter and Flush Control Register bit assignments
9.15. Integration Test Miscellaneous Output Register 0 bit assignments
9.16. Integration Test Trigger In and Flush In Acknowledge Register bit assignments
9.17. ETB for CoreSight Integration Register, ITTRFLIN bit assignments
9.18. Integration Test ATB Data Register 0 bit assignments
9.19. Integration Test ATB Control Register 2 bit assignments
9.20. Integration Test ATB Control Register 1 bit assignments
9.21. Integration Test ATB Control Register 0 bit assignments
9.22. CSTF Device ID bit assignments
9.23. ETB RAM size options
9.24. ETB11 and ETB comparison
10.1. Trace interface ports
10.2. Miscellaneous ports
10.3. Authentication interface ports
11.1. Trace out ports
11.2. SWO programmable registers
11.3. Lock Status Register bit assignments
11.4. Device ID Register bit assignments
11.5. Current Output Divisor Register bit assignments
11.6. Selected Pin Protocol Register bit assignments
11.7. Formatter and Flush Status Register bit assignments
11.8. Integration Test ATB Data Register 0 bit assignments
11.9. Integration Test ATB Control Register 2 bit assignments
11.10. Integration Test ATB Control Register 0 bit assignments
11.11. Manchester pin protocol encoding
11.12. UART pin protocol encoding
12.1. Sync packet encoding
12.2. Trace packet encoding
12.3. ITM packet priority levels
12.4. Miscellaneous ports
12.5. ITM programmable registers
12.6. Trace Enable Register bit assignments
12.7. Trace Trigger Register bit assignments
12.8. Control Register bit assignments
12.9. Synchronization Control Register bit assignments
12.10. Integration Test Trigger Out Acknowledge Register bit assignments
12.11. Integration Test Trigger Out Register bit assignments
12.12. Integration Test ATB Data Register 0 bit assignments
12.13. Integration Test ATB Control Register 2 bit assignments
12.14. Integration Test ATB Control Register 1 bit assignments
12.15. Integration Test ATB Control Register 0 bit assignments
12.16. Authentication interface ports
A.1. CoreSight DAP signals
A.2. CoreSight CTI signals
A.3. CoreSight CTM signals
A.4. CoreSight replicator signals
A.5. CoreSight synchronous bridge signals
A.6. CoreSight trace funnel signals
A.7. CoreSight TPIU signals
A.8. CoreSight ETB signals
A.9. CoreSight SWO signals
A.10. CoreSight ITM signals
B.1. CoreSight components and clock domains
C.1. Summary of pin names
C.2. 10-way connector for SWD or JTAG systems
C.3. 20-way connector for future SWD or JTAG systems
C.4. Generic signal definitions
D.1. Deprecated switching sequences
E.1. Differences between issue E and issue F
E.2. Differences between issue F and issue G
E.3. Differences between issue G and issue H

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The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

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Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

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Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A29 September 2004First release for r0p0.
Revision B24 March 2005Updated for r0p1. Programmers model revised.
Revision C31 July 2006Changed to CoreSight Components Technical Reference Manual. Serial Wire and JTAG (SWJ) information added to Chapter 3. Chapter 11 (SWV), Chapter 12 (SWO), Chapter 13 (ITM), and Appendix C (SWD and JTAG Trace Connector) added.
Revision D17 November 2006Block versions revised.
Revision E08 August 2007Alignment with ARM Debug Interface v5 Architecture Specification. Additional corrections and enhancements.
Revision F18 April 2008Block versions revised. Additional corrections and enhancements.
Revision G12 March 2009Updated for Serial Wire Debug multi-drop support. Additional corrections and enhancements.
Revision H10 July 2009Minor corrections and enhancements.
Copyright © 2004-2009 ARM. All rights reserved.ARM DDI 0314H
Non-Confidential