Using this book

Note

Details of CoreSight component memory maps, registers, and CoreSight component programmers models are in the relevant chapters.

This book is organized into the following chapters:

Chapter 1 Introduction

Read this for an overview of the CoreSight components. This chapter also lists and classifies all CoreSight components.

Chapter 2 Debug Access Port

Read this for a description of the Debug Access Port (DAP). The chapter gives an overview of the DAP and detailed descriptions of the following components:

  • SWJ-DP

  • JTAG-DP

  • SW-DP

  • JTAG-AP

  • AHB-AP

  • APB-AP

  • APB-multiplexor

  • ROM table.

Chapter 3 CoreSight Trace Sources

Read this for a brief description of two CoreSight trace sources, AHB Trace Macrocell (HTM) and CoreSight Embedded Trace Macrocells (ETMs).

Chapter 4 Embedded Cross Trigger

Read this for a description of the Embedded Cross Trigger (ECT). Contains ECT connectivity recommendations for cores and other components.

Chapter 5 ATB 1:1 Bridge

Read this for a description of the AMBA Trace Bus (ATB) 1:1 bridge.

Chapter 6 ATB Replicator

Read this for a description of the ATB replicator.

Chapter 7 CoreSight Trace Funnel

Read this for a description of the Trace Funnel.

Chapter 8 Trace Port Interface Unit

Read this for a description of the Trace Port Interface Unit (TPIU).

Chapter 9 Embedded Trace Buffer

Read this for a description of the Embedded Trace Buffer (ETB). Differences from other ETBs are listed at the end of this chapter.

Chapter 10 Serial Wire Viewer

Read this chapter for a description of the Serial Wire Viewer (SWV).

Chapter 11 Serial Wire Output

Read this chapter for a description of the Serial Wire Output (SWO).

Chapter 12 Instrumentation Trace Macrocell

Read this for a description of the Instrumentation Trace Macrocell (ITM).

Appendix A CoreSight Port List

Read this for a description of the CoreSight component signals.

Appendix B CoreSight Components and Clock Domains

Read this for a description of the CoreSight components and their respective clock domains.

Appendix C Serial Wire Debug and JTAG Trace Connector

Read this for a description of the SWD and JTAG trace connector used for debug targets.

Appendix D Deprecated SWJ-DP Switching Sequences

Read this for a description of the switching sequences used in earlier versions of the SWJ-DP.

Appendix E Revisions

Read this for a description of the technical changes between released issues of this book.

Glossary

Read this for definitions of terms used in this book.

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