The ETM ID Register, at offset 0x1E4, is
read-only. Figure 2.1 shows
the register bit assignments.
Table 2.2 shows
the value of the fields when reading the ID Register. The ID Register has
the value of 0x41001220.
Table 2.2. ETM ID Register bit assignments
| Bits | Value | Meaning |
|---|
| [31:24] | 0x41 | Implementor = A (ARM Limited). |
| [23:17] | b000000 | Reserved. |
| [16] | b0 | Load pc first. Special handling is not required
to reconstruct the data addresses of an LDM with the pc in the register
list because ETMv3.2 requires noncontiguous data addresses to be traced.
However, special handling is required to determine which transfers
correspond to which register. |
| [15:12] | b0001 | ARM core family = ARM9 processor. |
| [11:8] | b0010 | Major ETM architecture version number = 3. |
| [7:4] | b0010 | Minor ETM architecture version number = 2. |
| [3:0] | b0001 | Implementation revision. Value given is for
r0p1 release. |
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