CoreSight™ ETM9™ Technical Reference Manual 2.2. CoreSight ETM9 registers summary

2.2. CoreSight ETM9 registers summary

Table 2.1 lists the implementation-specific CoreSight ETM9 registers.

Table 2.1. CoreSight ETM9 registers summary

Name	Base offset	Type	Reset value	Description
Configuration Code	`0x004`	RO	`0x8D294024`	See Configuration Code Register.
ID	`0x1E4`	RO	`0x41001221`	See ETM ID Register.
Configuration Code Extension	`0x1E8`	RO	`0x000008A2`	See Configuration Code Extension Register.
ITMISCOUT	`0xEDC`	WO	-	See ITMISCOUT Register (miscellaneous outputs).
ITMISCIN	`0xEE0`	RO	-^[1]	See ITMISCIN Register (miscellaneous inputs).
ITTRIGGERACK	`0xEE4`	RO	-^a	See ITTRIGGERACK Register (trigger acknowledge).
ITTRIGGERREQ	`0xEE8`	WO	-	See ITTRIGGERREQ Register (trigger request).
ITATBDATA0	`0xEEC`	WO	-	See ITATBDATA0 Register (ATB data 0).
ITATBCTR2	`0xEF0`	RO	-^a	See ITATBCTR2 Register (ATB control 2).
ITATBCTR1	`0xEF4`	WO	-	See ITATBCTR1 Register (ATB control 1).
ITATBCTR0	`0xEF8`	WO	-	See ITATBCTR0 Register (ATB control 0).
Device Configuration	`0xFC8`	RO	0x00000000	Indicates no user-definable functionality. See the ETM Architecture Specification.
Device Type	`0xFCC`	RO	`0x00000013`	Indicates a processor trace source. See the ETM Architecture Specification.
Peripheral ID4	`0xFD0`	RO	`0x00000004`	See Peripheral Identification Registers.
Peripheral ID5	`0xFD4`	RO	`0x00000000`
Peripheral ID6	`0xFD8`	RO	`0x00000000`
Peripheral ID7	`0xFDC`	RO	`0x00000000`
Peripheral ID0	`0xFE0`	RO	`0x00000010`
Peripheral ID1	`0xFE4`	RO	`0x000000B9`
Peripheral ID2	`0xFE8`	RO	`0x000000XB`^[2]
Peripheral ID3	`0xFEC`	RO	`0x00000000`
Component ID0	`0xFF0`	RO	`0x0000000D`	See Component Identification Registers.
Component ID1	`0xFF4`	RO	`0x00000090`
Component ID2	`0xFF8`	RO	`0x00000005`
Component ID3	`0xFFC`	RO	`0x000000B1`
^[1]The values of these read-only registers depend on the signals on external pins of the CoreSight ETM9. Therefore it is not possible to define the register reset values. ^[2]See Peripheral Identification Registers for the value of X, bits [7:4] of the register value.

Note

For all other CoreSight ETM9 registers, see the ETM Architecture Specification.

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