CoreSight™ ETM9™ Technical Reference Manual 2.3.6. Integration Test Registers

2.3.6. Integration Test Registers

The following sub-sections describe the Integration Test Registers. If you want to access these registers you must first set bit[0] of the Integration Mode Control Register to 1.

You can use the write-only Integration Test Registers to set the outputs of some of the ETM signals. Table 2.7 lists the signals which can be controlled in this way.
You can use the read-only Integration Test Registers to read the state of some of the ETM input signals. Table 2.8 lists the signals which can be read in this way.

Table 2.7. Output signals that can be controlled by the Integration Test Registers

Signal	Register	Bit	Register description
AFREADYM^[1]	ITATBCTR0	[1]	See ITATBCTR0 Register (ATB control 0)
ATBYTESM[1:0]^a	ITATBCTR0	[9:8]	See ITATBCTR0 Register (ATB control 0)
ATDATAM[31, 23, 15, 7, 0]^a	ITATBDATA0	[4:0]	See ITATBDATA0 Register (ATB data 0)
ATIDM[6:0]^a	ITATBCTR1	[6:0]	See ITATBCTR1 Register (ATB control 1)
ATVALIDM^a	ITATBCTR0	[0]	See ITATBCTR0 Register (ATB control 0)
EXTINACK[3:0]	ITMISCOUT	[3:0]	See ITMISCOUT Register (miscellaneous outputs)
EXTOUT[1:0]	ITMISCOUT	[9:8]	See ITMISCOUT Register (miscellaneous outputs)
TRIGOUT^a	ITTRIGGERREQ	[0]	See ITTRIGGERREQ Register (trigger request)
^[1]These signals are only available with ETM9CS. Other signals are available with both ETM9CSSingle and ETM9CS

Table 2.8. Input signals that can be read by the Integration Test Registers

Signal	Register	Bit	Register description
AFVALIDM^[1]	ITATBCTR2	[1]	See ITATBCTR2 Register (ATB control 2)
ATREADYM^a	ITATBCTR2	[0]	See ITATBCTR2 Register (ATB control 2)
DBGACK	ITMISCIN	[4]	See ITMISCIN Register (miscellaneous inputs)
EXTIN[3:0]	ITMISCIN	[3:0]	See ITMISCIN Register (miscellaneous inputs)
EXTOUTACK[1:0]	ITMISCIN	[9:8]	See ITMISCIN Register (miscellaneous inputs)
TRIGOUTACK^a	ITTRIGGERACK	[0]	See ITTRIGGERACK Register (trigger acknowledge)
^[1]These signals are only available with ETM9CS. Other signals are available with both ETM9CSSingle and ETM9CS

Using the Integration Test Registers

The CoreSight ETM9 Integration Manual gives a full description of the use of the Integration Test Registers to check integration. In brief:

When bit 1 of the Integration Mode Control Register is set, values written to the write-only integration test registers map onto the specified outputs of CoreSight ETM9. For example, writing 0x3 to ITMISCOUT[9:8] causes EXTOUT[1:0] to take the value 0x3.
When bit 1 of the Integration Mode Control Register is set, values read from the read-only integration test registers correspond to the values of the specified inputs of CoreSight ETM9. For example, if you read ITMISCIN[9:8] you obtain the value of EXTOUTACK[1:0].

ITMISCOUT Register (miscellaneous outputs)

The ITMISCOUT Register, at offset 0xEDC, is write-only. Figure 2.5 shows the register bit assignments.

Figure 2.5. ITMISCOUT Register bit assignments

Table 2.9 lists the register bit assignments for the ITMISCOUT Register.

Table 2.9. ITMISCOUT Register bit assignments

Bits	Name	Function
[31:10]	-	Reserved. Write as zero.
[9:8]	EXTOUT	Drives the EXTOUT[1:0] external outputs.
[7:4]	-	Reserved. Write as zero.
[3:0]	EXTINACK	Drives the EXTINACK[3:0] external outputs.

ITMISCIN Register (miscellaneous inputs)

The ITMISCIN Register. at offset 0xEE0, is read-only. Figure 2.6 shows the register bit assignments.

Figure 2.6. ITMISCIN Register bit assignments

Table 2.10 lists the fields when reading the ITMISCIN Register. The value of these fields depend on the signals on the input pins when the register is read.

Table 2.10. ITMISCIN Register bit assignments

Bits	Name	Function
[31:10]	-	Reserved. Read undefined.
[9:8]	EXTOUTACT	Returns the value of the EXTOUTACK[1:0] external inputs.
[7:5]	-	Reserved. Read undefined.
[4]	DBGACK	Returns the value of the DBGACK external input.
[3:0]	EXTIN	Returns the value of the EXTIN[3:0] external inputs.

ITTRIGGERACK Register (trigger acknowledge)

The ITTRIGGERACK Register, at offset 0xEE4, is read-only. Figure 2.7 shows the register bit assignments.

Figure 2.7. ITTRIGGERACK Register bit assignments

Table 2.11 describes the field when reading the ITTRIGGERACK Register. The value of this field depend on the signal on the input pins when the register is read.

Table 2.11. ITTRIGGERACK Register bit assignments

Bits	Name	Function
[31:1]	-	Reserved. Read undefined.
[0]	TRIGOUTACK	Returns the value of the TRIGOUTACK external input.

ITTRIGGERREQ Register (trigger request)

The ITTRIGGERREQ Register, at offset 0xEE8, is write-only. Figure 2.8 shows the register bit assignments.

Figure 2.8. ITTRIGGERREQ Register bit assignments

Table 2.12 lists the register bit assignments for the ITTRIGGERREQ Register.

Table 2.12. ITTRIGGERREQ Register bit assignments

Bits	Name	Function
[31:1]	-	Reserved. Write as zero.
[0]	TRIGOUT	Drives the TRIGOUT external output.

ITATBDATA0 Register (ATB data 0)

The ITATBDATA0 Register, at offset 0xEEC, is write-only. Figure 2.9 shows the register bit assignments.

Figure 2.9. ITATBDATA0 Register bit assignments

Table 2.13 lists the register bit assignments for the ITATBDATA0 Register.

Table 2.13. ITATBDATA0 Register bit assignments

Bits	Name	Function
[31:5]	-	Reserved. Write as zero.
[4:0]	ATDATAM	Drives the ATDATAM[31, 23, 15, 7, 0] external outputs.

ITATBCTR2 Register (ATB control 2)

The ITATBCTR2 Register, at offset 0xEF0, is read-only. Figure 2.10 shows the register bit assignments.

Figure 2.10. ITATBCTR2 Register bit assignments

Table 2.14 lists the fields when reading the ITATBCTR2 Register. The value of these fields depend on the signals on the input pins when the register is read.

Table 2.14. ITATBCTR2 Register bit assignments

Bits	Name	Function
[31:2]	-	Reserved. Read undefined.
[1]	AFVALIDM	Returns the value of the AFVALIDM external input.
[0]	ATREADYM	Returns the value of the ATREADYM external input.

ITATBCTR1 Register (ATB control 1)

The ITATBCTR1 Register, at offset 0xEF4, is write-only. Figure 2.11 shows the register bit assignments.

Figure 2.11. ITATBCTR1 Register bit assignments

Table 2.15 lists the register bit assignments for the ITATBCTR1 Register.

Table 2.15. ITATBCTR1 Register bit assignments

Bits	Name	Function
[31:7]	-	Reserved. Write as zero.
[6:0]	ATIDM	Drives the ATIDM[6:0] external outputs.

ITATBCTR0 Register (ATB control 0)

The ITATBCTR0 Register, at offset 0xEF8, is write-only. Figure 2.12 shows the register bit assignments.

Figure 2.12. ITATBCTR0 Register bit assignments

Table 2.16 lists the register bit assignments for the ITATBCTR0 Register.

Table 2.16. ITATBCTR0 Register bit assignments

Bits	Name	Function
[31:10]	-	Reserved. Write as zero.
[9:8]	ATBYTESM	Drives the ATBYTESM[1:0] external outputs.
[7:2]	-	Reserved. Write as zero.
[1]	AFREADYM	Drives the AFREADYM external output.
[0]	ATVALIDM	Drives the ATVALIDM external output.

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