The physical interface for JTAG-DP and the relationship to
the signal references in the ARM Debug Interface v5 Architecture
Specification is given in Table 2.1. The interface does not include a return
clock signal. RTCK and the nTRST signals are optional because
this only relates to resetting the DBGTAP state machine which can
be performed by transmitting 5 TCK pulses
with TMS HIGH.
Table 2.1. JTAG-DP physical interface
| Implementation signal name (JTAG-DP) | ADIv5 signal name (JTAG-DP) | Direction | JTAG-DP signal description |
|---|
| TDI | DBGTDI | Input | Debug Data In |
| TDO | DBGTDO | Output | Debug Data Out |
| SWCLKTCK | TCK | Input | Debug Clock |
| SWDITMS | DBGTMS | Input | Debug Mode Select |
| nTRST | DBGTRSTn | Input | Debug TAP Reset |
Table 2.2 lists
all implemented registers accessible by JTAG-DP. All other IR instructions
are implemented as BYPASS and an external TAP controller must be implemented
in accordance with the ARM Debug Interface v5 Architecture Specification if
more IR registers are required, for example JTAG TAP boundary scan.
Table 2.2. JTAG-DP registers
| IR instruction value | JTAG-DP register | DR scan width | Description |
|---|
| b1000 | ABORT | 35 | JTAG-DP Abort Register (ABORT) |
| b1010 | DPACC | 35 | JTAG DP/AP Access Registers
(DPACC/APACC) |
| b1011 | APACC | 35 |
| b1110 | IDCODE | 32 | JTAG Device ID Code Register (IDCODE) |
| b1111 | BYPASS | 1 | JTAG Bypass Register (BYPASS) |
For more information about these registers, their features,
and how to access them, see the ARM Debug Interface v5
Architecture Specification. Implementation specific
detail is described in Common debug port features and registers.
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