CoreSight ™ DAP-Lite TechnicalReference Manual


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Conventions
Further reading
Feedback
Feedback on this product
Feedback on this book
1. Introduction
1.1. About the DAP-Lite
1.2. DAP-Lite structure
1.3. DAP-Lite control flow
1.4. DAP-Lite block summary
2. Functional Description
2.1. About the Debug Port
2.2. SWJ-DP
2.2.1. Structure of the SWJ-DP
2.2.2. Operation of the SWJ-DP
2.2.3. JTAG and SWD interface
2.2.4. Clock, reset and power domain support
2.2.5. SWD and JTAG selection mechanism
2.3. JTAG-DP
2.3.1. Overview
2.3.2. Implementation specific details
2.4. SW-DP
2.4.1. Overview
2.4.2. Implementation specific details
2.4.3. Transfer timings
2.5. Common debug port features and registers
2.5.1. Features overview
2.5.2. Example pushed operations
2.5.3. Debug Port registers overview
2.5.4. Implementation specific registers
2.6. Access ports
2.6.1. Overview
2.7. APB-AP
2.7.1. External interfaces
2.7.2. Implementation features
2.7.3. Programmer’s model overview
2.7.4. APB-AP Control/Status Word Register,CSW, 0x00
2.7.5. APB-AP Transfer Address Register,TAR, 0x04
2.7.6. APB-AP Data Read/Write Register, DRW,0x0C
2.7.7. APB-AP Banked Data Registers, BD0-BD3,0x10-0x1C
2.7.8. Debug APB ROM Address, ROM, 0xF8
2.7.9. APB-AP Identification Register
2.7.10. DAP transfers
2.8. APB-Mux
2.8.1. APB-Mux port definitions
2.8.2. APB-Mux miscellaneous signals
2.8.3. APB-Mux arbitration and connectivity
2.8.4. APB-Mux software access enable
2.8.5. APB-Mux clocks, power, and resets
2.9. ROM table
2.9.1. ROM table programmer’s model
2.9.2. ROM table entries
2.10. Authentication requirements
2.11. Clocks and resets
2.12. Connections to debug components andsystem interfaces
3. Programmer’s Model
3.1. About the programmer’s model
A. DAP-Lite Ports
A.1. CoreSight DAP signals
B. Revisions
Glossary

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ConfidentialityStatus

This document is Non-Confidential. The right to use, copyand disclose this document may be subject to license restrictionsin accordance with the terms of the agreement entered into by ARMand the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developedproduct.

Revision History
Revision A 06January 2006 First release.
Revision B 14December 2006 Second release.
Revision C 19October 2007 Alignment with ARM Debug Interfacev5 Architecture Specification. Additional corrections and enhancements.
Revision D 01May 2008 Fourth release.
Copyright © 2006 - 2008 ARM Limited. All rights reserved. ARM DDI 0316D
Non-Confidential