CoreSight ™ TPIU-Lite TechnicalReference Manual

Revision: r0p0

Table of Contents

About this manual
Product revision status
Intended audience
Using this manual
Further reading
Feedback on this product
Feedback on this manual
1. Introduction
1.1. About the TPIU-Lite
2. Functional Overview
2.1. TPIU-Lite structure
2.2. Trace out port
2.2.1. Synchronous trace port
2.2.2. Synchronous encoding pin protocol
2.2.3. Constraining the supported TRACEDATAport widths
2.3. Triggers
2.3.1. Output indication
2.3.2. Correlation with AFVALID
2.4. Flushing
2.5. Stopping trace
2.6. Bypass mode
2.7. TRACECLK generation
2.8. Authentication requirements
3. Programmer’s Model
3.1. About the programmer’s model
3.2. Register summary
3.3. Trace port control registers
3.3.1. Supported Port Size Register, 0x000
3.3.2. Current Port Size Register, 0x004
3.4. Formatter and flush registers
3.4.1. Formatter and Flush Status Register,0x300
3.4.2. Formatter and Flush Control Register,0x304
3.4.3. Formatter Synchronization CounterRegister, 0x308
3.5. Integration test registers
3.5.1. Integration Test Trigger In and FlushIn Acknowledge Register, 0xEE4
3.5.2. Integration Test Trigger In and FlushIn Register, 0xEE8
3.5.3. Integration Test ATB Data Register0, 0xEEC
3.5.4. Integration Test ATB Control Register2, 0xEF0
3.5.5. Integration Test ATB Control Register0, 0xEF8
3.6. CoreSight-defined registers
3.6.1. Integration Mode Control Register,0xF00
3.6.2. Claim Tag Set Register, 0xFA0
3.6.3. Claim Tag Clear Register, 0xFA4
3.6.4. Lock Access Register, 0xFB0
3.6.5. Lock Status Register, 0xFB4
3.6.6. Authentication Status Register, 0xFB8
3.6.7. Device ID Register, 0xFC8
3.6.8. Device Type Identifier Register, 0xFCC
3.6.9. Peripheral ID Registers, 0xFD0-0xFEC
3.6.10. Component ID Registers, 0xFF0-0xFFC
A. TPIU-Lite Ports
A.1. ATB port
A.2. Debug APB ports
A.3. Trace Out port
A.4. Miscellaneous TPIU-Lite ports

List of Tables

2.1. Example port configurations
2.2. Synchronous trace port pin encoding
2.3. Synchronous pin protocol
3.1. TPIU programmable registers
3.2. Formatter and Flush Status Register bit assignments
3.3. Formatter and Flush Control Register bit assignments
3.4. Formatter Synchronization Counter Register bit assignments
3.5. Integration Test Trigger In and Flush In Acknowledge Registerbit assignments
3.6. Integration Test Trigger In and Flush In Register bit assignments
3.7. Integration Test ATB Data Register 0 bit assignments
3.8. Integration Test ATB Control Register 2 bit assignments
3.9. Integration Test ATB Control Register 0 bit assignments
3.10. Integration Mode Control Register bit assignments
3.11. Claim Tag Set Register bit assignments
3.12. Claim Tag Clear Register bit assignments
3.13. Lock Access Register bit assignments
3.14. Lock Status Register bit assignments
3.15. Authentication Status Register bit assignments
3.16. Authentication Status Register pairs
3.17. Device ID Register bit assignments
3.18. Device Type Identifier Register bit assignments
3.19. Peripheral ID4 Register bit assignments
3.20. Peripheral ID0 Register bit assignments
3.21. Peripheral ID1 Register bit assignments
3.22. Peripheral ID2 Register bit assignments
3.23. Peripheral ID3 Register bit assignments
3.24. Component ID0 Register bit assignments
3.25. Component ID1 Register bit assignments
3.26. Component ID2 Register bit assignments
3.27. Component ID3 Register bit assignments
A.1. ATB slave ports
A.2. Debug APB ports
A.3. Trace Out port signals
A.4. Miscellaneous TPIU-Lite ports

Proprietary Notice

Words and logos marked with ® or ™ are registered trademarks or trademarksowned by ARM Limited. Other brands and names mentioned herein maybe the trademarks of their respective owners.

Neither the whole nor any part of the information containedin, or the product described in, this document may be adapted orreproduced in any material form except with the prior written permissionof the copyright holder.

The product described in this document is subject to continuousdevelopments and improvements. All particulars of the product andits use contained in this document are given by ARM in good faith.However, all warranties implied or expressed, including but notlimited to implied warranties of merchantability, or fitness forpurpose, are excluded.

This document is intended only to assist the reader in theuse of the product. ARM Limited shall not be liable for any lossor damage arising from the use of any information in this document,or any error or omission in such information, or any incorrect useof the product.


This document is Non-Confidential. The right to use, copyand disclose this document may be subject to license restrictionsin accordance with the terms of the agreement entered into by ARMand the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developedproduct.

Revision History
Revision A 6January 2006 First release for r0p0
Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0317A