CoreSight™ ETM11™ Technical Reference Manual B.2. ETM11CS I/O timing parameters

B.2. ETM11CS I/O timing parameters

Signals are classified according to the percentage of the clock period taken up by internal logic.

For inputs this is the delay between the input port and the first register.
For outputs this is the delay between the last register and the output port.

The timing classifications used are:

Early: Less than 20% of the period described above.
Middle: Between 20% and 80% of the period described above.
Late: Greater than 80% of the period described above.

Table B.2 describes the ETM11CS signal timing parameters.

Table B.2. ETM11CS signal timing parameters

Signal name	Timing classification	Input/ Output
AFREADYM	Middle	Output
AFVALIDM	Middle	Input
ASICCTL[7:0]	Middle	Output
ATBYTESM[1:0]	Middle	Output
ATCLK	-	Input
ATCLKEN	Middle	Input
ATDATAM[31:0]	Middle	Output
ATIDM[6:0]	Middle	Input
ATREADYM	Middle	Input
ATRESETn	Late	Input
ATVALIDM	Middle	Output
CFGBIGEND	Middle	Input
CLK	-	Input
CORESELECT[2:0]	Middle	Output
DBGACK	Middle	Input
DBGEN	Middle	Input
ETMCPADDRESS[14:0]	Middle	Input
ETMCPCOMMIT	Middle	Input
ETMCPENABLE	Middle	Input
ETMCPSECCTL[1:0]	Middle	Input
ETMCPWDATA[31:0]	Middle	Input
ETMCPWRITE	Middle	Input
ETMDA[31:3]	Middle	Input
ETMDACTL[17:0]	Middle	Input
ETMDD2[63:0]	Middle	Input
ETMDDCTL2[1:0]	Middle	Input
ETMDBGRQ	Middle	Output
ETMDD[63:0]	Middle	Input
ETMDDCTL[3:0]	Middle	Input
ETMEN	Middle	Output
ETMIA[31:0]	Middle	Input
ETMIACTL[17:0]	Middle	Input
ETMIARET[31:0]	Middle	Input
ETMIASECCTL[1:0]	Middle	Input
ETMPADV[2:0]	Middle	Input
ETMPWRUP	Middle	Output
ETMWFIPENDING	Middle	Input
ETPSUP	Late	Input
EVNTBUS[19:0]	Middle	Input
EXTIN[3:0]	Middle	Input
EXTINACK[3:0]	Middle	Output
EXTOUT[1:0]	Middle	Output
EXTOUTACK[1:0]	Middle	Input
EXTSBYPASS	Middle	Input
FIFOPEEK[8:0]	Middle	Output
MAXCORES[2:0]	Middle	Input
MAXEXTIN[2:0]	Middle	Input
MAXEXTOUT[1:0]	Middle	Input
MAXPORTSIZE[3:0]	Middle	Input
nCORECLAMP	Late	Input
nETMWFIREADY	Middle	Output
NIDEN	Middle	Input
nPORESET	Late	Input
nSOCCLAMP	Late	Input
PADDRDBG[11:2]	Middle	Input
PADDRDBG31	Middle	Input
PCLKDBG	Middle	Input
PCLKENDBG	Middle	Input
PENABLEDBG	Middle	Input
PORTMODE[2:0]	Middle	Output
PORTSIZE[3:0]	Middle	Output
PRDATADBG[31:0]	Middle	Output
PREADYDBG	Middle	Output
PRESETDBGn	Late	Input
PSELDBG	Middle	Input
PSLVERRDBG	Middle	Output
PWDATADBG[31:0]	Middle	Input
PWRITEDBG	Middle	Input
RSTBYPASS	Late	Input
SE	Late	Input
THUMB2EN	Late	Input
TRIGOUT	Middle	Output
TRIGOUTACK	Middle	Input
TRIGSBYPASS	Middle	Input
TRUSTZONEEN	Late	Input

Note

Actual clock frequencies and input and output timing constraints vary according to application requirements and the silicon process technologies used. The maximum operating clock frequencies change according to the constraints and the process technology you use.

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