This chapter contains implementation-specific information relating to the CoreSight ETM11. It contains the following sections:
ETM architecture version
CoreSight ETM11 registers summary
CoreSight ETM11 register descriptions
Precise TraceEnable events
Parallel instruction execution
Support for independent load/store units
Context ID tracing
Interaction with the Performance Monitoring Unit, PMU
ETM11CSSingle clocks
ETM11CSSingle resets
ETM11CS clocks
ETM11CS resets
PORTMODE, PORTSIZE and MAXPORTSIZE
Data instructions in Java state
Restrictions and limitations.