| PCLKDBG | Input | Clock source | APB Clock |
| PCLKENDBG | Input | Clock source | APB Clock enable. Tie HIGH when not in use. |
| PRESETDBGn | Input | System reset generator | APB Bus Reset, active LOW |
| PADDRDBG[11:0] | Input | Debug APB | APB address bus |
| PADDRDBG31 | Input | Debug APB | APB address bus bit 31 (lock bypass access
mode) |
| PWRITEDBG | Output | Debug APB | When HIGH indicates an APB write access and
when LOW a read access |
| PENABLEDBG | Output | Debug APB | The enable signal is used to indicate the second
and subsequent cycles of a APB transfer |
| PWDATADBG[31:0] | Output | Debug APB | The write bus is driven by the APB Master during
write cycles (when PWRITEDBG is
HIGH) |
| PRDATADBG[31:0] | Input | Debug APB | The read bus is driven by the selected slave
(such as a CoreSight component) during read cycles (when PWRITEDBG is LOW) |
| PREADYDBG | Output | Debug APB | The ready signal used by the slave to extend
an APB transfer |
| PSLVERRDBG | Output | Debug APB | Error response of the Debug APB interface |
| PSELDBG | Input | Debug APB | Select HTM registers |
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