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The additional logic for functional verification and production testing enables:
capture of HTM input signals to the block
stimulation of the HTM output signals.
The integration vectors provide a way of verifying that the trace interface of the HTM is correctly wired into a system. This is done by separately testing four groups of signals:
These are tested by register access tests, which can verify the connections of all the address and data bits.
These are tested by register access tests, which can verify the connections of all the address and data bits.
These are tested by an example AHB capture, which can verify the connections of all the data bits. Additional test logic is added for testing of flush interface connection.
The tests for these signals are system-specific, and enable you to write the necessary tests. Additional logic is implemented enabling you to read and write to each intra-chip input/output signal.
Table 6.1 shows the test methods for the HTM signal groups.
Table 6.1. Test method for HTM signal connections
| Signal group | Signals | Test method |
|---|---|---|
| APB bus | PCLK, PCLKENDBG, PRESETDBGn, PSELDBG, PADDRDBG, PENABLEDBG, PWRITEDBG, PWDATADBG, PRDATADBG, PREADYDBG, PSLVERRDBUG | APB register access test. |
| AHB bus | HCLK, HRESETn, HTMHRESETn HADDR, HWRITE, HTRANS, HSIZE, HBURST, HPROT, HMASTER, HDOMAIN, HMASTLOCK, HUNALIGN, HBSTRB, HRDATAL, HRDATAH, HWDATAH, HWDATAH, HRESP, HREADY, HSEL | Example AHB capture. |
| ATB bus | ATCLK, ATCLKEN, ATRESETn | Example AHB capture. |
| ATVALIDM, ATREADYM, ATDATAM, ATBYTESM, AFREADYM, AFVALIDM, ATIDM | Example AHB capture and integration test registers. | |
| Intra-Chip | HTMSYNCBYPASS | Read from HTMSTATUS Register. |
| HTMMAXBUS | Read from HTMCFGCODE2 Register. | |
| HTMBUSSELECT | Output only. Test depends on SoC implementation. | |
| HTMASICCTRL | Output only. Test depends on SoC implementation. | |
| HTMTRIGGER, HTMTRIGOUTACK | Integration test registers. | |
| HTMEXTIN | Integration test registers. | |
| HTMEXTOUT | Output only. Test depends on SoC implementation. | |
| HTMSPNIDEN, HTMNIDEN, HTMDBGEN, HTMSPIDEN | Read only. For security reasons these signals must not be changed by integration logic. | |
| HTMTRACEDISABLE | Integration test registers. |
Test registers control these test features. This enables you to test the trace interface of the HTM in isolation from the rest of the system using only transfers from the AHB
A global register called HTMITCR must be activated before any integration tests can be performed. The HTMITCR register contains the ITEN bit, which is set to 1 during integration testing.
Figure 6.1 shows the integration logic.