During a single cycle the FIFO can receive up to 18 bytes, and sends out up to four bytes. The input and output ports are controlled by two separate clock signals that can be asynchronous to each other. During operation, address, auxiliary, and data packets are appended to the current contents of the FIFO. If the FIFO is almost full, just lower than the programmed FIFO level, only address packets are stored. Data suppression is deactivated when the space left in the FIFO is larger than the programmed level.

The implementation of the FIFO is based on a circular buffer, but the operation can be illustrated with a simple FIFO model as shown in Figure Introduction.4.

Figure Introduction.4. HTM FIFO operation

Data is continuously shifted out by the ATB interface, four bytes at a time. If there are less than four bytes in the FIFO, the FIFO waits for more data before transmitting data, except for the case of a flush operation on the ATB bus, when the remaining data in the FIFO is output. Flushing the FIFO can only be done through the ATB interface or by setting the PROG bit in the HTMCONTROL register.

If there is not enough room in the FIFO for additional bytes, the packet is dropped and an overflow packet is output to indicate a loss of trace.

When the PROG bit is set in the HTMCONTROL Register, the HTM trace operation is stopped but the FIFO contents and ATB operation are unaffected.

See Chapter 4 Protocol Details for details of packets.