AMBA ™ AHB Trace Macrocell(HTM) Technical Reference Manual

Revision: r0p4


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Conventions
Further reading
Feedback
Feedback on this product
Feedback on this book
Introduction. Introduction
Introduction.1. About the CoreSight AHB Trace Macrocell(HTM)
Introduction.2. HTM used in a CoreSight system
Introduction.3. Structure of the HTM
Introduction.3.1. Clocks and resets in HTM
Introduction.3.2. Data buses
Introduction.4. HTM features
Introduction.4.1. Register access lock
Introduction.4.2. Security pins
Introduction.4.3. Security and software protection
Introduction.4.4. ASIC control output
Introduction.4.5. Bus select output
Introduction.4.6. ARM11 AHB extensions
Introduction.4.7. Unsupported signals
Introduction.4.8. Power saving and clamping logic
Introduction.5. HTM functional description
Introduction.5.1. HTM operations
Introduction.5.2. FIFO operation
Introduction.5.3. External trace disabling
2. Functional Description
2.1. HTM structure
2.2. HTM trace control block
2.3. HTM idle status
2.4. HTM trace generation blocks
2.5. HTM resources
2.5.1. Internal event bus
2.5.2. Boolean combinations for definingevents
2.5.3. Resource identification
2.6. HTM primary resources
2.6.1. Single address comparators
2.6.2. Address range comparators
2.6.3. AMBA control comparators
2.6.4. External inputs
2.7. HTM derived resources
2.7.1. Counter resources
2.7.2. External outputs
2.7.3. Sequencer
2.7.4. Trace start/stop control
2.8. HTM trace filtering
2.8.1. External Trace Disable and Software Trace Disable
2.9. HTM trigger unit
2.10. Endianness support and bus width support
2.10.1. Endianness support
2.10.2. Bus width support
3. Programmer’s Model
3.1. About the programmer’s model
3.1.1. APB interface
3.1.2. Programming resources
3.2. HTM register summary
3.2.1. HTM registers
3.3. HTM detailed register descriptions
3.3.1. HTM Global Control Register, HTMGLBCTRL
3.3.2. HTM Status Register, HTMSTATUS
3.3.3. HTM Configuration Code Register, HTMCFGCODE
3.3.4. HTM Configuration Code 2 Register,HTMCFGCODE2
3.3.5. HTM Control Register, HTMCONTROL
3.3.6. HTM Trigger Event Register, HTMTRIGEVT
3.3.7. HTM Trigger Status Register, HTMTRIGSTATE
3.3.8. HTM AUX Select Register, HTMAUXSEL
3.3.9. HTM Synchronization Counter ReloadRegister, HTMSYNCRELOAD
3.3.10. HTM Synchronization Counter ValueRegister, HTMSYNCCOUNT
3.3.11. HTM FIFO Level Register, HTMFIFOLEVEL
3.3.12. HTM Trace Enable START STOP Register,HTMSTARTSTOP
3.3.13. HTM TraceEnable Control 2 Register,HTMTCTRL2
3.3.14. HTM TraceEnable Event Register, HTMTRACEEVT
3.3.15. HTM TraceEnable Control Register,HTMTRACECTRL
3.3.16. HTM Start/Stop Status Register, HTMSSTATE
3.3.17. HTM ASIC Control Register, HTMASICCTRL
3.3.18. HTM Bus Select Register, HTMBUSSELECT
3.3.19. HTM Address Comparator Value Registers,HTMADDR0-15
3.3.20. HTM Address Type Registers, HTMADDRTYPE0-15
3.3.21. HTM AMBA Control Select Registers,HTMHCTRLSEL0-7
3.3.22. HTM AMBA Control Compare Value Registers,HTMHCTRLVAL0-7
3.3.23. HTM AMBA Control Compare Mask Registers,HTMHCTRLMASK0-7
3.3.24. HTM Counter Reload Value Registers,HTMCNTRELDVAL0-3
3.3.25. HTM Counter Enable Registers, HTMCNTENABLE0-3
3.3.26. HTM Counter Reload Event Registers,HTMCNTRELDEVT0-3
3.3.27. HTM Counter Value Registers, HTMCNTVALUE0-3
3.3.28. HTM Sequencer Transition Event Registers,HTMSEQEVT0-5
3.3.29. HTM Sequencer State Register, HTMSEQSTATE
3.3.30. HTM External Output Event Registers,HTMEXTOUTEVT0-3
3.3.31. HTM ATB ID Register, HTMATIDOUT
3.3.32. HTM Claim Tag Set Register, HTMCLAIMTAGSET
3.3.33. HTM Claim Tag Clear Register, HTMCLAIMTAGCLR
3.3.34. HTM Lock Access Register, HTMLOCK_ACCESS
3.3.35. HTM Lock Status Register, HTMLOCK_STATUS
3.3.36. HTM Authentication Status Register,HTMAUTHSTATUS
3.3.37. HTM Device CoreSight ID Register,HTMDEVID
3.3.38. HTM ATB Device Type Register, HTMDEV_TYPE
3.4. Peripheral Identification Registers,HTMPERIPHID0-7
3.4.1. HTM Peripheral ID0 Register, HTMPERIPHID0
3.4.2. HTM Peripheral ID1 Register, HTMPERIPHID1
3.4.3. HTM Peripheral ID2 Register, HTMPERIPHID2
3.4.4. HTM Peripheral ID3 Register, HTMPERIPHID3
3.4.5. HTM Peripheral ID4 Register, HTMPERIPHID4
3.4.6. HTM Peripheral ID5 Register, HTMPERIPHID5
3.4.7. HTM Peripheral ID6 Register, HTMPERIPHID6
3.4.8. HTM Peripheral ID7 Register, HTMPERIPHID7
3.4.9. Identification fields
3.5. Identification Registers, HTMPCOMPONID0-3
3.5.1. HTM Component ID0 Register, HTMCOMPONID0
3.5.2. HTM Component ID1 Register, HTMCOMPONID1
3.5.3. HTM Component ID2 Register, HTMCOMPONID2
3.5.4. HTM Component ID3 Register, HTMCOMPONID3
4. Protocol Details
4.1. ATB interface outputs
4.2. Trace bandwidth reduction
4.2.1. Data suppression
4.2.2. FIFO overflow
4.3. ATB packet format
4.3.1. Header encoding summary
4.3.2. A-sync packet
4.3.3. Trigger packet
4.3.4. Sequential address packet
4.3.5. Ignore packet
4.3.6. Trace off packet
4.3.7. Data suppressed packet
4.3.8. FIFO overflow packet
4.3.9. AHB reset packets
4.3.10. CycleCount packet
4.3.11. Data packet
4.3.12. Address packet
4.3.13. Auxiliary packet
4.4. Data extraction
4.5. HTM trace data output rules
4.6. HTM packet generation
4.6.1. HTM typical burst transfer
4.6.2. HTM typical burst but data is not traced
4.6.3. HTM address excluded during burst
4.6.4. Address wrap handling
4.6.5. Data suppressed
4.6.6. Data suppress inside a burst
4.6.7. Data suppressed for single transfers
4.6.8. FIFO overflow (trace lost)
4.6.9. TraceOff control
4.7. Cycle-accurate trace
4.8. Reconstruction of timing information
4.8.1. Address, data, and auxiliary packets
4.8.2. Reset On/Off packets and TraceOffpacket
4.8.3. Trigger packet
4.9. Cycle timing characteristics of ATBpackets and signals
4.10. Synchronizing trace
4.11. Bandwidth limitations
5. Implementation-specific Characteristics
5.1. HTM64 and HTM32 features summary
5.2. CoreSight registers
5.2.1. CoreSight management registers
5.2.2. Peripheral and component identificationregisters
5.2.3. Integration test registers
5.2.4. Configuration code register
5.3. HTM clocks and resets
5.4. HTM restrictions
6. Programmer’s Model for Test
6.1. HTM test harness overview
6.1.1. Integration test for AHB and ATB connections
6.2. Scan testing
6.3. Test registers
6.3.1. HTM Test Control Register, HTMITCR
6.3.2. ATB Control Integration Test Register0, HTMITATBCTR0
6.3.3. ATB Control Integration Test Register1, HTMITATBCTR1
6.3.4. ATB Control Integration Test Register2, HTMITATBCTR2
6.3.5. ATB Data Integration Test Register0, HTMITATBDATA0
6.3.6. Cycle Counter Test Register, HTMITCYCCOUNT
6.3.7. External Trace Disable IntegrationTest Register, HTMITTRACEDIS
6.3.8. Trigger Output Integration Test Register,HTMITTRIGGER
6.3.9. Trigger Output Acknowledge IntegrationTest Register, HTMITTRIGOUTACK
6.3.10. External Input Integration Test Register,HTMITEXTIN
A. Signal Descriptions
A.1. HTM signals
A.2. HTM ATB signals
A.3. HTM external signals
A.4. HTM APB signals
A.5. HTM scan test control signals
A.6. Power-down indication signals andclamping logic
A.6.1. Power domains
A.6.2. HTM signal behavior on power-down
A.6.3. HTM power-down behavior
B. Troubleshooting
B.1. Troubleshooting the HTM
C. Revisions
Glossary

List of Figures

1. Key to timing diagram conventions
Introduction.1. HTM in an exampleCoreSight system
Introduction.2. HTM block diagram
Introduction.3. Example use of HTMBUSSELECT
Introduction.4. HTM FIFO operation
2.1. HTM security andcontrol signals
2.2. HTM detailed blockdiagram with clock domains
2.3. HTM APB interfacesignals
2.4. HTM AHB interfacesignals
2.5. HTM ATB interfacesignals
2.6. Idle status state machine
2.7. State machine structure in HTM
2.8. Programming HTM registers
2.9. HTM resources
2.10. Internal event bus resource encoding
2.11. Sequencer state diagram
2.12. TraceEnable signal generation logic
2.13. HTM trigger unit
3.1. HTMGLBCTRL Registerbit assignments
3.2. HTMSTATUS Registerbit assignments
3.3. HTMCFGCODE Registerbit assignments
3.4. HTMCFGCODE2 Registerbit assignments
3.5. HTMCONTROL Registerbit assignments
3.6. HTMTRGEVT Registerbit assignments
3.7. HTMTRIGSTATE Registerbit assignments
3.8. HTMAUXSEL Registerbit assignments
3.9. HTMSYNCRELOADRegister bit assignments
3.10. HTMSYNCCOUNT Registerbit assignments
3.11. HTMFIFOLEVEL Registerbit assignments
3.12. HTM STARTSTOPRegister bit assignments
3.13. HTMCTRL2 Registerbit assignments
3.14. HTMTRACEEVT Registerbit assignments
3.15. HTMTRACECTRL Registerbit assignments
3.16. HTMSSTATE Registerbit assignments
3.17. HTMASICCTRL Register bit assignments
3.18. HTMASICCTRL exampleuse
3.19. HTMBUSSELECT Registerbit assignments
3.20. HTMADDRTYPE Registerbit assignments
3.21. Single address match with overlappingaddress windows
3.22. Second single address matching example
3.23. Single address non-matching example
3.24. Address range comparison successfulmatch example 1
3.25. Address range comparison successfulmatch example 2
3.26. Address range comparison unsuccessfulmatch example 1
3.27. Address range comparison unsuccessfulmatch example 2
3.28. HTMHCTRLSEL Register bit assignments
3.29. SEL values andAMBA control comparators
3.30. HTMHCTRLVAL Registerbit assignments
3.31. HTMHCTRLMASK Registerbit assignments
3.32. HTMCNTRELDVALRegister bit assignments
3.33. HTMCNTENABLE Registerbit assignments
3.34. HTMCNTRELDEVTRegister bit assignments
3.35. HTMCNTVALUE Registerbit assignments
3.36. HTMSEQEVT Registerbit assignments
3.37. HTMSEQSTATE Registerbit assignments
3.38. HTMEXTOUTEVT Registerbit assignments
3.39. HTMATIDOUT Registerbit assignments
3.40. HTMCLAIMTAGSET Register bit assignments
3.41. HTMCLAIMTAGCLR Register bit assignments
3.42. HTMLOCK_STATUSRegister bit assignments
3.43. HTMAUTHSTATUS Register bit assignments
3.44. HTMDEV_TYPE Registerbit assignments
3.45. HTMPERIPHID0 Register bit assignments
3.46. HTMPERIPHID1 Register bit assignments
3.47. HTMPERIPHID2 Register bit assignments
3.48. HTMPERIPHID3 Register bit assignments
3.49. HTMPERIPHID4 Register bit assignments
4.1. HTM packets
4.2. HTM data packet length
4.3. HTM A-sync packet
4.4. HTM trigger packet
4.5. HTM sequential address packet
4.6. HTM ignore packet
4.7. HTM trace offpacket
4.8. HTM data suppressedpacket
4.9. HTM FIFO overflowpacket
4.10. AHB reset on packet
4.11. AHB reset off packet
4.12. HTM CycleCount packet
4.13. HTM data packet bit values
4.14. HTM address packet bit values
4.15. HTM auxiliary packet
4.16. HTM typical operations and packets
4.17. HTM packet rearrangement
4.18. HTM typical burst operations andpackets generated
4.19. HTM typical burst operations wheredata is not traced
4.20. HTM address packet excluded duringburst
4.21. HTM wrap burst with address excluded
4.22. HTM use of data suppressed packets
4.23. Data suppressed packet inside a burst
4.24. Data suppressed packets in a singletransfer
4.25. Lost trace and use of FIFO overflowpacket
4.26. TraceOff operation
4.27. Use of CycleCount packet for timing-accuratetrace
4.28. Additional CycleCount packet to showgaps in transfers
4.29. CycleCount packet after trace resumes
4.30. Use of CycleCount packet in transferswith no wait state
4.31. Time measurement with CycleCountpacket
4.32. Delays from AHB bus activities totrace generation
4.33. Delay of AHB Reset activities totrace generation
4.34. Delay of trigger activities to tracegeneration
4.35. Synchronizing compression
6.1. Integration logic
6.2. HTMITCR register bit assignments
6.3. HTMITATBCTR0 Register bit assignments
6.4. HTMITATBCTR1 Register bit assignments
6.5. HTMITATBCTR2 Register bit assignments
6.6. HTMITATBDATA0 Register bit assignments
6.7. HTMITTRACEDIS Register bit assignments
6.8. HTMITTRIGGER Register bit assignments
6.9. HTMITTRIGOUTACK Register bit assignments
6.10. HTMITEXTIN Register bit assignments
A.1. Clamping logic and power-down indicationsignals

List of Tables

Introduction.1. HTM reset signal descriptions
Introduction.2. Security pin values and HTM tracing behavior
2.1. Boolean function encoding for events
2.2. Event encoding
2.3. Resource encodings
2.4. HTM resource identification encoding
2.5. BUSENDIAN values and endianness
3.1. Summary of HTM registers
3.2. CoreSight management registers
3.3. Peripheral and component identification registers
3.4. HTMGLBCTRL Register bit assignments
3.5. HTMSTATUS Register bit assignments
3.6. HTMCFGCODE Register bit assignments
3.7. HTMCFGCODE2 Register bit assignments
3.8. HTMCONTROL Register bit assignments
3.9. HTMTRIGEVT Register bit assignments
3.10. HTMTRIGSTATE Register bit assignments
3.11. HTMAUXSEL Register bit assignments
3.12. Auxiliary packet key
3.13. SELCODE encodings
3.14. Auxiliary packet second byte values
3.15. Auxiliary packet first byte values
3.16. HTMSYNCRELOAD Register bit assignments
3.17. HTMSYNCCOUNT Register bit assignments
3.18. HTMCONTROL Register bit assignments
3.19. HTMSTART STOP Register bit assignments
3.20. HTMCTRL2 Register bit assignments
3.21. HTMTRACEEVT Register bit assignments
3.22. HTMTRACECONTROL Register bit assignments
3.23. HTMSSTATE Register bit assignments
3.24. HTMASICCTRL Register bit assignments
3.25. HTMBUSSELECT Register bit assignments
3.26. HTMADDR Register bit assignments
3.27. HTMADDRTYPE Register bit assignments
3.28. SIZE field with HSIZE
3.29. HTMHCTRLSEL Register bit assignments
3.30. SEL values key
3.31. HTMHCTRLVAL Registers bit assignments
3.32. HTMHCTRLMASK Register bit assignments
3.33. HTMCNTRELDVAL Register bit assignments
3.34. HTMCNTENABLE Register bit assignments
3.35. HTMCNTRELDEVT Register bit assignments
3.36. HTMCNTVALUE Register bit assignments
3.37. HTMSEQEVT0-5 Register bit assignments
3.38. HTMSEQEVT Register bit assignments
3.39. HTMSEQSTATE Register bit assignments
3.40. HTMEXTOUTEVT Register bit assignments
3.41. HTMATIDOUT Register bit assignments
3.42. HTMCLAIMTAGSET Register bit assignments
3.43. HTMCLAIMTAGCLR Register bit assignments
3.44. HTMLOCK_ACCESS Register bit assignments
3.45. HTMLOCK_STATUS Register bit assignments
3.46. Effect of PADDRDBG31 on registers
3.47. HTMAUTHSTATUS Register bit assignments
3.48. HTMDEVID Register bit assignments
3.49. HTMDEV_TYPE Register bit assignments
3.50. HTMPERIPHID0 Register bit assignments
3.51. HTMPERIPHID1 Register bit assignments
3.52. HTMPERIPHID2 Register bit assignments
3.53. HTMPERIPHID3 Register bit assignments
3.54. HTMPERIPHID4 Register bit assignments
3.55. HTMCOMPONID0 Register bit assignments
3.56. HTMCOMPONID1 Register bit assignments
3.57. HTMCOMPONID2 Register bit assignments
3.58. HTMCOMPONID3 Register bit assignments
4.1. HTM data length encodings
4.2. HTM header encodings summary
4.3. Resp encodings
4.4. HTM data extraction with HUNALIGN 0 and BUSWIDTH 1
4.5. HTM data extraction with HUNALIGN 0 and BUSWIDTH 0
4.6. HTM data extraction with HUNALIGN 1 and BUSWIDTH 1
4.7. Data extraction with HUNALIGN 1 and BUSWIDTH 0
4.8. Cycle timing characteristics of ATB packets and signals
5.1. HTM features for HTM64 and HTM32
5.2. Bus sizes and HTM read and write data bus signals
5.3. CoreSight management registers
5.4. Peripheral and component identification registers
5.5. HTM integration test registers
6.1. Test method for HTM signal connections
6.2. HTM integration test registers
6.3. HTMITCR register bit assignments
6.4. HTMITATBCTR0 Register bit assignments
6.5. HTMITATBCTR1 Register bit assignments
6.6. HTMITATBCTR2 Register bit assignments
6.7. HTMITATBDATA0 Register bit assignments
6.8. HTMITCYCCOUNT Register bit assignments
6.9. HTMITTRACEDIS Register bit assignments
6.10. HTMITTRIGGER Register bit assignments
6.11. HTMITTRIGOUTACK Register bit assignments
6.12. HTMITEXTIN Register bit assignments
A.1. HTM AHB signals
A.2. HTM ATB signals
A.3. HTM external signals
A.4. HTM APB signals
A.5. HTM scan test control signal
A.6. HTM signal behavior on assertion of power down
A.7. Accessible HTM registers in power down
B.1. HTM typical problems and suggested remedies
C.1. Differences between issue D and issue E

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ConfidentialityStatus

This document is Non-Confidential. The right to use, copyand disclose this document may be subject to license restrictionsin accordance with the terms of the agreement entered into by ARMand the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developedproduct.

Revision History
Revision A 30September 2004 First release
Revision B 22March 2005 Updated for r0p1. Programmer’s modelrevised.
Revision C 17November 2006 Updated for r0p2. Idle status added.
Revision D 11June 2007 Updated for r0p3.
Revision E 18April 2008 Updated for r0p4.
Copyright © 2004-2008 ARM Limited. All rights reserved. ARM DDI 0328E
Non-Confidential