3.2. Summary of registers

Table 3.1 shows the register map for the cache controller.

Table 3.1. Cache controller register map

RegisterReadsWritesSecure
0System ID and Cache TypeIgnoredNS
1ControlControlWrite S Read NS/S
2Interrupt/Counter ControlInterrupt/Counter ControlNS
3-6ReservedReserved-
7Cache Maintenance OperationsCache Maintenance OperationsSecure bit of access effects operation
8ReservedReserved-
9Cache LockdownCache LockdownSecure bit of access effects operation
10-14ReservedReserved-
15Test and DebugTest and DebugWrite S Read S

All register addresses in the Cache Controller are fixed relative to the base address. Table 3.2 shows the registers in base offset order.

Table 3.2. Summary of Cache Controller registers

RegisterName

Base

offset

Type

Reset

value

Description
r0Cache ID0x000RO0x41000086[1]Register 0,Cache ID Register
r0Cache Type0x004RO0x1C100100Register 0,Cache Type Register
r1Control0x100RW0x00000000Register 1,Control Register
r1Auxiliary Control0x104RW0x02020FFFRegister 1, Auxiliary Control Register
r2Event Counter Control0x200RW0x00000000Register 2, Event Counter Control Register Register 2, Event Counter Control Register
r2Event Counter1 Configuration0x204RW0x00000000Register 2, Event Counter0 Configuration Register
r2Event Counter0 Configuration0x208RW0x00000000Register 2, Event Counter0 Configuration Register
r2Event Counter1 Value0x20CRW0x00000000Register 2, Event Counter1 Value Register
r2Event Counter0 Value0x210RW0x00000000Register 2, Event Counter1 Value Register
r2Interrupt Mask[2]0x214RW0x00000000Register 2, Interrupt Mask Register
r2 Masked Interrupt Status[2]0x218RO0x00000000Register 2, Masked Interrupt Status Register
r2Raw Interrupt Status[2]0x21CRO0x00000000Register 2, Raw Interrupt Status Register
r2Interrupt Clear[2]0x220WO0x00000000Register 2, Interrupt Clear Register
r7Cache Sync0x730RW0x00000000Register 7, Cache Maintenance Operations
r7Invalidate Line By PA0x770RW0x00000000Register 7, Cache Maintenance Operations
r7Invalidate by Way0x77CRW0x00000000Register 7, Cache Maintenance Operations
r7Clean Line by PA0x7B0RW0x00000000Register 7, Cache Maintenance Operations
r7Clean Line by Index/Way0x7B8RW0x00000000Register 7, Cache Maintenance Operations
r7Clean by Way0x7BCRW0x00000000Register 7, Cache Maintenance Operations
r7Clean and Invalidate Line by PA0x7F0RW0x00000000Register 7, Cache Maintenance Operations
r7Clean and Invalidate Line by Index/Way0x7F8RW0x00000000Register 7, Cache Maintenance Operations
r7Clean and Invalidate by Way0x7FCRW0x00000000Register 7, Cache Maintenance Operations
r9Lockdown by Way - D Side0x900RW0x00000000Register 9, Cache Lockdown
r9Lockdown by Way - I Side0x904RW0x00000000Register 9, Cache Lockdown
r15Test Operation0xF00RW0x00000000Register 15, Test and Debug
r15Line Data (8 × Word)

0xF10,

0xF14,

0xF18,

0xF1C,

0xF20,

0xF24,

0xF28,

and

0xF2C

RWNot resetRegister 15, Test and Debug
r15Line Tag {Tag, V, D0, D1, RR}0xF30RWNot resetRegister 15, Test and Debug
r15Debug Control Register0xF40RW0x00000000Register 15, Test and Debug

[1] This value is L220 pin dependent, depending on how external CACHEID pins are tied.

[2] The cache interrupt registers are those that can be accessed by secure and NS operations.

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