3.3.15. Register 9, Cache Lockdown

The Cache Lockdown Register is a read-write register. This register prevents new addresses being allocated and also prevents the data in the set ways from being evicted. It also enables the cache controller to filter data from instructions or data transactions. Cache lockdown is controlled by the Cache Lockdown Register 9. It is implemented as two lockdown subregisters, one for data and one for instructions. These registers have read-only or read write permission, depending on the security you have selected for the register access and on the Non-Secure Lockdown Enable bit in the Auxiliary Control Register. Table 3.18 shows the different settings of the Cache Lockdown Register.

Table 3.18. Cache lockdown

Security of the register accessNon-Secure Lockdown Enable bitPermission
Secure0 the default value, or 1Read and Write
Non-Secure0 the default value, or 1Read only Read and write

On reset the Non-Secure Lockdown Enable bit is set to 0 and Lockdown Registers are not permitted to be modified by NS accesses. In that configuration, if a NS access tries to write to those registers, the write response returns a DECERR response. This decode error results in the registers not being updated.

When permitted, the NS lockdown functionality can be identical to the secure one.

To only use selected cache Ways within a SET, Lockdown format C, defined by the ARM Architecture Reference Manual provides a method to restrict the replacement algorithm used on cache linefills, read this section for more information. Using this method, you can fetch code or load data into the L2 cache and protect it from being evicted. Alternatively the method can be used to reduce cache pollution. See Figure 3.16. The 32-bit ADDR cache address consists of the following fields: < TAG > < INDEX > < WORD > < BYTE >

Whenever the cache lookup occurs, the Index defines where in the cache ways to look, and the number of ways defines the number of locations with the same Index. This is called a Set. Therefore an 8-way set associative cache has eight locations where an address with INDEX (A) can exist.


The number of locations are also known as lines.

If the cache lookup misses and a cache linefill is required, there are eight possible locations where the new line can be placed. Lockdown format C restricts the cache replacement algorithm to only use a subset of the eight possible locations. The locking configurability is listed in Table 3.19 and Table 3.20. To apply lockdown, set to 1’b1 for each bit to lock each respective Way. For example, set Bit [0] for Way 0, Bit [1] for Way 1.

Table 3.19. Data Lockdown Register - offset 0x900

[31:8]ReservedSBZ / RAZ
[7:0]DATALOCKSet to 1’b1 for each bit to lock each respective Way.

Table 3.20. Instruction Lockdown Register - offset 0x904

[31:8]ReservedSBZ / RAZ
[7:0]INSTRLOCKSet to 1b1 for each bit to lock each respective Way.

Fetching code or loading data into the L2 cache

Use lockdown format C in the following cases:

  1. To make sure the selected way is unlocked, for example, unlock Way 0.

  2. Loading code or data into the cache on Way 0.

  3. Writing to the lockdown register to prevent filling to Way 0, but enable filling to Ways 1-7. The code/data is now protected in the cache and is not evicted on allocation.

Preventing and/or reducing cache pollution

There are benefits of having a critical piece of software or data being cached in the Cache Controller with out it being polluted or evicted, because of a new allocation. Using lockdown format C provides a simple method to load data into the Cache Controller through the linefill mechanism, then locking the cache memory to prevent eviction, and finally using the L220 cache maintenance operations to efficiently clean the data to the main memory system.

To do that:

  1. Use lockdown format C, I and/or D lockdown, to restrict the permitted ways for cache filling to n-ways, where n is less than the total number of ways. For example, only permit filling to way 0.

  2. Cache code or data into the cache

    • Fetch code into the cache by executing the routine for the first time

    • Load data into the cache by:

      • loading data for the first time

      • cache the data in L2 by executing the read loop being cached at L1 only

  3. Write to the Lockdown Register, I and/or D lockdown, to prevent allocation to WAY 0, but to enable allocation to WAYS 1-7. The code/data is now protected in the cache and is not evicted on a linefill.

Example using a lockdown format C for the cache controller

There can be benefits in processing large frame buffers in the cache controller, and making them appear as if there is a large amount of restricted physically addressed space available in fast memory. Because the cache controller is 8-way set associative, using lockdown format C provides a simple method to load data into the cache controller using the linefill mechanism, lock the cache memory to prevent eviction, then use the cache controller cache maintenance operations to efficiently clean the data to the main memory system.

For example, if you require a 1MB Frame Buffer in the 2MB 8-way set associative cache controller, in a system using the ARM1176JZ(F)-S processor:

  1. Set the address page attributes so the L1 is noncacheable and the L2 page is cacheable.

  2. Set the L220 lockdown to only fill to Ways 0-3, this is equivalent to 1MB.

  3. The 1MB is now contiguously mapped over 4 Ways of 256k each.

  4. Load data into the L220 cache by executing a load routine in the ARM processor, where a series of LDRs are issued, a cache line apart from one another. The L1 attribute is noncacheable, so the L1 cache is not polluted. The L2 cache attribute is cacheable, so the Cache Controller performs linefills, filling into Ways 0-3. The linefill buffer provides efficient filling.

  5. When finished, set the L220 lockdown to lock Ways 0-3, and only permit filling to Ways 4-7, this is equivalent to 1MB.

The L2 cache now contains a 1MB frame buffer, and 1MB of 4-way associative cache. Lookups and reads/writes can occur to the entire 2MB, but the frame buffer is prevented from being evicted. L220 cache maintenance operations can be used to efficiently clean to main memory. When the frame buffer is no longer required, Ways 0-3 can be unlocked, and are overwritten by normal cache behavior.

Lockdown format C has a pattern-matching field, so any of the eight ways can be locked. There is no requirement to start at 0 and work up. If all ways are marked as being locked, then nothing is allocated.


It is recommended that the cache lockdown register is modified with a read-modify-write sequence.

Replacement strategy

The cache controller uses a pseudo-random replacement strategy. A deterministic replacement strategy can be achieved, when you use them in combination with the lockdown registers.

The pseudo-random replacement strategy fills empty, unlocked ways first. If a line is completely full, the victim is chosen as the next unlocked way.

If you require a deterministic replacement strategy, the lockdown registers are used to prevent ways from being allocated. For example, if the L2 size is 256KB, and each way is 32KB, and a piece of code is required to reside in two ways of 64KB, with a deterministic replacement strategy, then ways 1-7 must be locked before the code is filled into the L2 cache. If the first 32KB of code is allocated into way 0 only, then way 0 must be locked and way 1 unlocked so that the second half of the code can be allocated in way 1.

There are two lockdown registers, one for data and one for instructions, if so required, you can separate data and instructions into separate ways of the L2 cache.

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