3.3.1. Register 0,Cache ID Register
This is a read-only register and returns the 32-bit device
ID code. This register reads off the CACHEID input
bus, the value specified by system integrator.
Figure 3.1 shows
the register bit assignments.
Table 3.3 shows
the register bit assignments.
Table 3.3. Register 0,Cache ID bit assignments
| Bits | Name | Description |
|---|
| [31:24] | Implementor | 0x41 (ARM) |
| [23:16] | Reserved | SBZ |
| [15:10] | CACHE ID | - |
| [9:6] | Part number |
0x2
|
| [5:0] | RTL release | 0x6 |
Note
Part number 0x2 denotes
ARM L220 Level 2 Cache Controller
RTL release 0x6 denotes r1p7-01rel0
RTL code of the Cache Controller. Refer to the Release Note accompanying
the release of the L220 Cache Controller to find out the value of
these bits for other releases
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