L220 Cache Controller Technical Reference ManualRevision: r1p7
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2.2.3. Exported AXI control

Table 2.8 provides information on the AXI control signals that are exported on the master ports of the cache controller.

Table 2.8. Exported master ports AXI control signals

Access typeMaster control signals busesValue (Verilog)
Noncacheable read transactions, nonbufferable write transactions, or cache disabled

AWCACHEMx, ARCACHEMx

AWSIDEBANDMx, ARSIDEBANDMx

AWPROTMx, ARPROTMx

AWLOCKMx, ARLOCKMx

all as original transaction
Linefills associated with a RAARCACHEMx as original transaction
ARSIDEBANDMx{5’b00000}
ARPROTMxas original transaction
ARLOCKMx{2’b00}
WA Linefill ARCACHEM1 {4'b1010}
ARSIDEBANDM1{5’b00000}
ARPROTM1{1’b0,SECURITY,1’b1}
ARLOCKM1{2’b00}
All bufferable write transactionsAWCACHEM1 {4'b0010}
AWSIDEBANDM1{5’b00000}
AWPROTM1{1’b0,SECURITY,1’b1}
AWLOCKM1{2’b00}
EvictionsAWCACHEM1 {4'b0011}
AWSIDEBANDM1{5’b00000}
AWPROTM1{1’b0,SECURITY,1’b1}
AWLOCKM1{2’b00}

Note

SECURITY denotes the value of the NS attribute stored with the data.

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