L220 Cache Controller Technical Reference ManualRevision: r1p7
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2.2.9. RAM interfaces

This section describes the following:

Data RAM

The data RAM shown in Figure 2.4 is organized as 8 ways 256-bit wide contiguous memories. It supports the following accesses:

  • 8 word data reads

  • n * 8 bits data writes with byte enables controls

  • 8 word data writes for linefills.

Figure 2.4. Data RAM organization

Dirty RAM

The dirty RAM shown in Figure 2.5 is organized as a 16-bit wide memory, 2 bits per 8-word cache line. The dirty RAM address is the same as the tag RAM address bus. It supports the following accesses:

  • 16 bit dirty reads for write-back eviction on a linefill

  • 16 bit dirty reads for cache maintenance operations

  • 1 or 2 bit dirty writes for writes and allocations.

Figure 2.5. Dirty RAM organization

Figure 2.6 shows the dirty RAM connectivity.

Figure 2.6. Dirty RAM connectivity

Tag RAM

The tag RAM is shown in Figure 2.7. There is one tag RAM for each way of the L2 cache. A tag RAM is organized as a 21-bit wide memory. 18 bits are dedicated to address tag, 1 bit for security information, 1 bit for valid information, and optionally 1 bit for parity. The tag RAM address bus is also the address bus for the dirty RAM. The tag RAM support the following accesses:

  • 20-bit tag reads for Tag lookup

  • 20-bit tag writes for allocations.

The NS bit takes the value of 1 for NS data, and 0 for secure data.

Note

You require a 21-bit wide memory to support the parity option.

Figure 2.7. Tag RAM organization

Cache lookup

Figure 2.8 shows the tag RAM format:

Figure 2.8. Tag RAM format

Each line is marked as secure or NS depending on the value of the AWPROT[1] or ARPROT[1] value on the original transaction. The security setting of the access, AWPROT[1] or ARPROT[1], is used for Cache Lookup and compared with the NS attribute in the Tag.

The tag RAM contains a field to hold the NS attribute bit corresponding for each cache line. This is required so that the NS attribute bit for all cache ways is compared to generate the cache hit.

Note

  • The cache is not automatically flushed when the processor changes security state.

  • If an access is performed, and has an AWPROT[1]/ARPROT[1] value of 1'b1, then the NS attribute must be HIGH. Cache lookups are performed on lines marked as NS, the NS cache line attribute = 1, according to Physical Address (PA).

  • If any access is performed in secure state, and the transaction has an AWPROT[1]/ARPROT[1] value of 1'b0), then the NS attribute must be LOW. Cache lookups are performed on lines marked as secure (NS cache line attribute = 0) according to PA. A secure access only hits on tags with a secure NS attribute.

RAM sizes

Table 2.22 shows the RAM sizes.

Table 2.22. RAM sizes

L2 cache sizeData RAMTag RAMDirty RAM
128KB1 × (256 + 32) × (ways × 512)Ways × (20 + 1) × 5121 × (2 × ways) × 512
256KB1 × (256 + 32) × (ways × 1024)Ways × (19 + 1) × 1,0241 × (2 × ways) × 1,024
512KB1 × (256 + 32) × (ways × 2048)Ways × (18 + 1) × 2,0481 × (2 × ways) × 2,048
1MB1 × (256 + 32) × (ways × 4096)Ways × (17 + 1) × 4,0961 × (2 × ways) × 4,096
2MB1 × (256 + 32) × (ways × 8192)Ways × (16 + 1) × 8,1921x (2 × ways) × 8,192

Note

  • The format for RAM sizes are:

    • Number of RAM × (width + parity) × number of address location

  • The dirty ram does not have parity. Width for the tag RAM consists of Valid + NS + address.

RAM bus usage versus cache associativity and way size

This section covers:

  • Data RAM usage

  • Dirty RAM usage

  • Tag RAM usage.

Data RAM usage

Figure 2.9 shows the DATAADDR bus format:

Figure 2.9. Data RAM address bus format

Bits [15:13] connections depend on the cache associativity:

  • 1 or 2 way associative:

    • Bits [15:14] are left unconnected.

      Bit 13 is the Most Significant Bit (MSB) of the RAM address bus.

  • 3 or 4 way associative:

    • Bit 15 is left unconnected.

      Bits [14:13] are the MSB of the RAM address bus.

  • 5 to 8 way associative: Bits [15:13] are the MSB of the RAM address bus.

Bits [12:0] depend on the way size:

  • 16KB way size:

    • Bits [12:9] are left unconnected.

      Bits [8:0] are the Least Significant Bits (LSB) of the RAM address bus.

  • 32KB way size:

    • Bits [12:10] are left unconnected.

      Bits [9:0] are the LSB of the RAM address bus.

  • 64KB way size:

    • Bits [12:11] left unconnected.

      Bits [10:0] are the LSB of the RAM address bus.

  • 128KB way size:

    • Bit 12 is left unconnected.

      Bits [11:0] are the LSB of the RAM address bus.

  • 256KB way size:

    • Bits [12:0] are the LSB of the RAM address bus.

All bits of the data bus are always connected.

Dirty RAM usage

Depending on the way size, some bits of the TAGADDR bus are not used for the dirty RAM address:

  • 16KB way size:

    • Bits [12:9] are left unconnected.

      Bits [8:0] are the LSB of the RAM address bus.

  • 32KB way size:

    • Bits [12:10] are left unconnected.

      Bits [9:0] are the LSB of the RAM address bus.

  • 64KB way size:

    • Bits [12:11] are left unconnected.

      Bits [10:0] are the LSB of the RAM address bus.

  • 128KB way size:

    • Bit 12 is left unconnected.

      Bits [11:0] are the LSB of the RAM address bus.

  • 256KB way size:

    • Bits [12:0] are the LSB of the RAM address bus.

Depending on the cache associativity, some bits of DIRTYRD bus must be tied low and some bits of DIRTYWD are left unconnected:

  • 1 way associative:

    • Bits [1:0] of DIRTYRD and DIRTYWD used for data busses.

      Bits [15:2] of DIRTYD must be tied LOW.

  • 2 way associative:

    • Bits [3:0] of DIRTYRD and DIRTYWD used for data busses.

      Bits [15:4] of DIRTYD must be tied LOW.

  • 3 way associative:

    • Bits [5:0] of DIRTYRD and DIRTYWD used for data busses. Bits [15:6] of DIRTYD must be tied LOW.

  • 4 way associative:

    • Bits [7:0] of DIRTYRD and DIRTYWD used for data buses.

      Bits [15:8] of DIRTYD must be tied LOW.

  • 5 way associative:

    • Bits [9:0] of DIRTYRD and DIRTYWD used for data busses. Bits [15:10] of DIRTYD must be tied LOW.

  • 6 way associative:

    • Bits [11:0] of DIRTYRD and DIRTYWD used for data busses.

      Bits [15:12] of DIRTYD must be tied LOW.

  • 7 way associative:

    • Bits [13:0] of DIRTYRD and DIRTYWD used for data busses.

      Bits [15:2] of DIRTYD must be tied LOW.

  • 8 way associative:

    • All bits [1:0] of DIRTYRD and DIRTYWD used for data busses.

Tag RAM usage

TAGADDR and TAGRDn/TAGWDn buses usage depends on the way size:

  • 16KB way size:

    • Bits [12:9] of TAGADDR are left unconnected.

      Bits [8:0] are the RAM address bus. All bits of TAGRDn and TAGWDn are used for data busses.

  • 32KB way size:

    • Bits [12:10] of TAGADDR are left unconnected. Bits [9:0] are the RAM address bus.

      Bits [19:1] of TAGRDn and TAGWDn are used for data buses.

      Bit 0 of TAGRDn must be tied LOW.

  • 64KB way size:

    • Bits [12:11] of TAGADDR are left unconnected.

      Bits [10:0] are the RAM address bus. All bits of TAGRDn and TAGWDn are used for data buses.

      Bits [1:0] of TAGRDn must be tied LOW.

  • 128KB way size:

    • Bit 12 of TAGADDR is left unconnected.

      Bits [11:0] are the RAM address bus.

      Bits [19:4] of TAGRDn and TAGWDn are used for data busses.

      Bits [2:0] of TAGRDn must be tied LOW.

  • 256KB way size:

    • Bits [12:0] are the RAM address bus.

      Bits [19:4] of TAGRDn and TAGWDn are used for data busses.

      Bits [3:0] of TAGRDn must be tied LOW.

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