L220 Cache Controller Technical Reference ManualRevision: r1p7
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L220 Cache Controller Technical Reference Manual

Revision: r1p7

Copyright © 2004-2007 ARM Limited. All rights reserved.

Proprietary notices

Table of Contents

Preface
About this manual
Product revision status
Intended audience
Using this manual
Conventions
Further reading
Feedback
Feedback on this product
Feedback on this manual
1. Introduction
1.1. About the Cache Controller
1.1.1. Features
1.2. Typical system configuration
1.3. Peripheral port connectivity with r1
1.4. Product revisions
1.4.1. r0p0 to r1p0
1.4.2. r1p0 to r1p1
1.4.3. r1p1 to r1p2
1.4.4. r1p2 to r1p3
1.4.5. r1p3 to r1p4
1.4.6. r1p4 to r1p5
1.4.7. r1p5 to r1p7
2. Functional Overview
2.1. Functional description
2.1.1. Clock enable usage model in the Cache Controller AXI interfaces
2.1.2. Master and slave interfaces
2.1.3. AXI peripheral port interface
2.1.4. TrustZone support
2.1.5. AXI low-power interface
2.1.6. Internal registers
2.1.7. Buffers
2.1.8. Data RAM
2.1.9. Tag RAM
2.1.10. Dirty RAM
2.2. Functional operation
2.2.1. AXI master and slave interfaces
2.2.2. AXI transaction ordering
2.2.3. Exported AXI control
2.2.4. AXI peripheral port interface operation
2.2.5. TrustZone support in the cache controller
2.2.6. Power modes
2.2.7. Implementation details
2.2.8. Data RAM configuration
2.2.9. RAM interfaces
3. Programmer’s Model
3.1. About the programmer’s model
3.1.1. Configuration and control registers
3.2. Summary of registers
3.3. Register descriptions
3.3.1. Register 0,Cache ID Register
3.3.2. Register 0,Cache Type Register
3.3.3. Register 1,Control Register
3.3.4. Register 1, Auxiliary Control Register
3.3.5. Register 2, Event Counter Control Register
3.3.6. Register 2, Event Counter1 Configuration Register
3.3.7. Register 2, Event Counter0 Configuration Register
3.3.8. Register 2, Event Counter1 Value Register
3.3.9. Register 2, Event Counter0 Value Register
3.3.10. Register 2, Interrupt Mask Register
3.3.11. Register 2, Masked Interrupt Status Register
3.3.12. Register 2, Raw Interrupt Status Register
3.3.13. Register 2, Interrupt Clear Register
3.3.14. Register 7, Cache Maintenance Operations
3.3.15. Register 9, Cache Lockdown
3.3.16. Register 15, Test and Debug
A. Signal Descriptions
A.1. Clock and reset
A.2. Configuration
A.3. Slave, peripheral and master ports
A.3.1. Slave port 0
A.3.2. Slave port 1
A.3.3. Peripheral port
A.3.4. Master port 0
A.3.5. Master port 1
A.4. RAM interface
A.4.1. Data RAM interface
A.4.2. Tag RAM interface
A.4.3. Dirty RAM interface signals
A.5. Cache event monitoring
A.6. Cache interrupt
A.7. MBIST interface
B. AC Parameters
B.1. Reset and configuration signal timing parameters
B.2. Slave port 0 I/O signal timing parameters
B.3. Slave port 1 I/O signal timing parameters
B.4. Peripheral slave port signal timing parameters
B.5. Master port 0 I/O signal timing parameters
B.6. Master port 1 I/O signal timing parameters
B.7. RAMs signal timing parameters
B.7.1. Data RAM
B.7.2. Tag RAM
B.7.3. Dirty RAM
B.8. Event monitor signal timing parameters
B.9. Cache interrupt ports signal timing parameters
B.10. MBIST interface signal timing parameters
C. Timing Diagrams
C.1. Single read hit transaction
C.2. Single read miss transaction
C.3. Two simultaneous read hits
C.4. Single noncacheable read transaction
C.5. Single bufferable write transaction
C.6. Single nonbufferable write transaction
Glossary

List of Figures

1. key to timing diagram conventions
1.1. Top level diagram
1.2. Example L220 Cache Controller interfaced to an ARM processor
1.3. Top level view showing ARM processor and peripheral port connectivity
2.1. Internal data paths
2.2. AXI peripheral port interface
2.3. L220 parity and RAM error support
2.4. Data RAM organization
2.5. Dirty RAM organization
2.6. Dirty RAM connectivity
2.7. Tag RAM organization
2.8. Tag RAM format
2.9. Data RAM address bus format
3.1. Register 0, Cache ID bit assignments
3.2. Register 0,Cache Type bit assignments
3.3. Register 1,Control bit assignments
3.4. Auxiliary Control Register
3.5. Compiled RAM Latency
3.6. Event Counter Control Register bit assignments
3.7. Event Counter1 Configuration Register bit assignments
3.8. Event Counter0 Configuration Register bit assignments
3.9. Interrupt Mask Register bit assignments
3.10. Masked Interrupt Status Register bit assignments
3.11. Raw Interrupt Status Register bit assignments
3.12. Interrupt Clear Register bit assignments
3.13. Cache Sync Register assignment
3.14. Physical address format
3.15. Index way combination format
3.16. Format C lockdown
3.17. Test Operation Register
3.18. Cache data line organization
3.19. Line Tag Register format
3.20. L2 Debug Control Register
C.1. Single read hit transaction
C.2. Single read miss transaction
C.3. Two simultaneous read hits
C.4. Single noncacheable read transaction
C.5. Single bufferable write transaction
C.6. Single nonbufferable write transaction

List of Tables

1.1. Typical memory sizes and access times
1.2. Master port transactions for a two master port system
1.3. Master port transactions for a one master port system
2.1. AXI master interface attributes
2.2. AXI slave interface attributes
2.3. AWCACHE and ARCACHE definitions
2.4. Operational behavior descriptions
2.5. Caching policy changes when exclusive cache is enabled
2.6. Differences of cache controller pipeline behavior for exclusive configuration
2.7. Master Port ID values
2.8. Exported master ports AXI control signals
2.9. Address encoding bits
2.10. Cache controller cache configurability
2.11. Error responses for all combinations of L3 access
2.12. Event pins
2.13. Interrupts
2.14. Cacheable read requests on AXI slave ports
2.15. Write-through/write-back write access from WB
2.16. AXI M0 and AXI M1 masters or write-allocate buffer allocation requests
2.17. Clean maintenance operation cases
2.18. Invalidate maintenance operation cases
2.19. Clean and Invalidate maintenance operation cases
2.20. Cache controller data RAM sizes
2.21. Cache size and cache controller RAM Interface data
2.22. RAM sizes
3.1. Cache controller register map
3.2. Summary of Cache Controller registers
3.3. Register 0,Cache ID bit assignments
3.4. Register 0,Cache Type bit assignments
3.5. Register 1,Control bit assignments
3.6. Auxiliary Control Register
3.7. Event Counter Control Register bit assignments
3.8. Event Counter1 Configuration Register bit assignments
3.9. Event Counter0 Configuration Register bit assignments
3.10. Event Counter 1 Value Register bit assignments
3.11. Event Counter 0 Value Register bit assignments
3.12. Interrupt Mask Register bit assignments
3.13. Masked Interrupt Status Register bit assignments
3.14. Raw Interrupt Status Register bit assignments
3.15. Interrupt Clear Register bit assignments
3.16. Maintenance operations
3.17. Cache maintenance operations
3.18. Cache lockdown
3.19. Data Lockdown Register - offset 0x900
3.20. Instruction Lockdown Register - offset 0x904
3.21. Test Operation Register
3.22. Line Tag Register format
3.23. Debug Control Register bit assignments
A.1. Clock and reset signals
A.2. Configuration signals
A.3. Slave port 0
A.4. Slave port 1
A.5. Peripheral port
A.6. Master port 0
A.7. Master port 1
A.8. Data RAM interface signals
A.9. Tag RAM interface
A.10. Dirty RAM interface signals
A.11. Cache event monitoring signals
A.12. Cache Interrupt signals
A.13. MBIST interface signals
B.1. Reset and configuration
B.2. Slave port 0 I/O
B.3. Slave port 1 I/O
B.4. Peripheral slave port
B.5. Master port 0 I/O
B.6. Master port 1 I/O
B.7. Data RAM
B.8. Tag RAM
B.9. Dirty RAM
B.10. Event monitor
B.11. Cache interrupt ports
B.12. MBIST interface signal

Proprietary Notice

Words and logos marked with ® or ™ are registered trademarks or trademarks of ARM Limited in the EU and other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.

Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A09 August 2004First release.
Revision B12 November 2004Update for r1p0. No change in description of functionality.
Revision C10 December 2004Update for r1p1. No change in description of functionality.
Revision D28 January 2005Update for r1p2. Added description for bit [12] in Register 1, Auxiliary Control Register on page 3‑10.
Revision E02 August 2005Update for r1p3. No change in description of functionality.
Revision F19 December 2005Update for r1p4. No change in description of functionality.“Exclusive cache operation” changed to “exclusive cache configuration” throughout.Timing diagram appendix added.
Revision G01 March 2006Additions to error response table and clarification of use of C bit in Register 7. Part number corrected, timing diagrams updated.Security Override Check feature redefined. L220CLAMP added to Table A‑2 on page A‑3.
Revision H04 May 2006Update for r1p5. Peripheral Port behavior redefined.Table 2‑1 on page 2‑9 and Table 2‑2 on page 2‑10, AXI attributes tables, added.Exclusive cache configuration on page 2‑15 rewritten for clarity.Timing diagram Single bufferable write transaction on page C‑6 updated
Revision I08 September 2006Update for r1p7. Clock enable usage model changed.
Revision J22 February 2007Updated to correct defects. No change in description of functionality.
Revision K30 October 2007Correction to Cache Synchronization description in Background line operations on page 3‑23.
Revision L14 December 2007Amend Cache Synchronization description in Background line operations on page 3‑23.
Copyright © 2004-2007 ARM Limited. All rights reserved.ARM DDI 0329L
Non-Confidential
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