2.1.1.  MBIST Controller interface

The L220 MBIST Controller has one MBIST port, see Appendix A Signal Descriptions. Only one RAM is accessed by the L220 MBIST Controller at any time.

The MBIST Controller must be able to account for the different latencies of the RAMs. You can configure RAM latencies for the L220 Cache Controller RAMS. You can configure the following RAMs for up to eight cycles of latency:

See also L220 Compiled RAM Latencies.

You can use the MBIST Controller for testing the L220 Cache Controller compiled RAMs. You can also choose to design your own MBIST Controller. You can only access one RAM by the MBIST port at a time.

The Tag Parity RAM, if present, is tested at the same time as the Tag RAMs. Parity bits are considered as an extra bit on the Tag Data Bus.

Figure 2.1 shows the interfaces between the L220 MBIST Controller and the RAMs that MBIST tests.

Figure 2.1. L220 Cache Controller MBIST and RAM Interfaces

This section describes RAM latencies and the four MBIST RAM tests:

L220 Compiled RAM Latencies

The L220 Cache Controller resets assuming the slowest compiled RAMs are being used. This means eight L220 Cache Controller clock cycles are used for each access. In terms of reads, this means that the read data is sampled eight clock edges after the edge on which the read request is sampled by the RAM. Using this nomenclature, the shortest latency is one. During functional mode, the latencies for each RAM are programmed in the L220 Cache Controller Auxiliary Control Register. For MBIST, you must know the latencies of the RAMs being tested. The MBIST Controller defaults to one cycle of latency, but must reprogram this during the instruction load before MBIST testing can begin. The latency of the current RAM being tested is passed to the L220 MBIST Controller in the MBIST instruction. Table 2.1 shows the L220 Cache Controller compiled RAM latency.

Table 2.1. L220 Cache Controller compiled RAM Latency

Latency bits [2:0]Cycles of latency
3’b0001 cycle of latency. No additional latency. This is the default.
3’b0012 cycles of latency.
3’b0103 cycles of latency.
3’b0114 cycles of latency.
3’b1005 cycles of latency.
3’b1016 cycles of latency.
3’b1107 cycles of latency.
3’b1118 cycles of latency.

Figure 2.2 shows the L220 Cache Controller compiled RAM latency.

Figure 2.2. L220 Cache Controller compiled RAM Latency

MBIST testing of L220 Cache Controller data RAM

The L220 Cache Controller data RAM is 256 bits wide, and the size of the MBISTDIN and MBISTDOUT buses on the L220 Cache Controller MBIST interface is 64 bits, so four reads and four writes are required for each index of the data RAM. The L220 Cache Controller handles this by using the MBISTADDR[1:0] signal as a doubleword select for each index of the data RAM for writes. For reads from a previous MBIST transaction you use the MBISTDCTL[1:0] signal. You require separate pins because the MBIST transactions are pipelined. The MBIST Controller takes into account the data RAM latency and issues the correct control signals. Table 2.2shows the address range of the MBISTADDR bus used to test the data RAM, based on the L2 cache size and configured to be 8-way.

Table 2.2. MBISTADDR and MBISTDIN mapping for data RAM, 8-way

L2 cache size Number of data RAM indexes MBISTADDR to data RAM mapping MBISTDIN to data RAM mapping
128KB 4,096 DATAADR[11:0]=MBISTADDR[17:15,10:2] DATAWD[63:0]=MBISTDIN[63:0]
256KB 8,192 DATAADDR[12:0]=MBISTADDR[17:15,11:2] DATAWD[63:0]=MBISTDIN[63:0]
512KB 16,384 DATAADDR[13:0]=MBISTADDR[17:15,12:2] DATAWD[63:0]=MBISTDIN[63:0]
1MB 32,768 DATAADDR[14:0]=MBISTADDR[17:15,13:2] DATAWD[63:0]=MBISTDIN[63:0]
2MB 65,536 DATAADDR[15:0]=MBISTADDR[17:2] DATAWD[63:0]=MBISTDIN[63:0]

For a 4-way cache, you can remove one bit from the upper address range and add it to the lower address range as compared to an 8-way cache of the same size. Table 2-3shows the address range of the MBISTADDR bus used to test the data RAM, based on the L2 cache size and configured to be 4-way.

Table 2.3. MBISTADDR and MBISTDIN mapping for data RAM, 4-way

L2 cache sizeNumber of data RAM indexesMBISTADDR to data RAM mappingMBISTDIN to data RAM mapping
128KB4,096DATAADDR[11:0]=MBISTADDR[16:15,11:2]DATAWD[63:0]=MBISTDIN[63:0]
256KB8,192DATAADDR[12:0] =MBISTADDR[16:15,12:2]DATAWD[63:0] = MBISTDIN[63:0]
512KB16,384DATAADDR[13:0] =MBISTADDR[16:15,13:2]DATAWD[63:0] = MBISTDIN[63:0]
1MB32,768DATAADDR[14:0]=MBISTADDR[16:2]DATAWD[63:0] = MBISTDIN[63:0]

Note

A 2M 4-way cache is not possible because the L220 Cache Controller maximum way size is limited to 256KB.

The L220 Cache Controller has a Line Read Buffer (LRB), in each slave these are 256 bits wide. One of these holds data for MBIST testing. The L220 Cache Controller always adds two register delays to the MBIST data read path for the data RAM.

When using the L220 MBIST Controller you must account for the data RAM latency in the pipeline. The latency can be from one to eight clock cycles. See L220 Compiled RAM Latencies. The signal MBISTCE[0] is for the chip enable to the data RAM. The signal MBISTDCTL[2:0] is for reads from previous MBIST transactions.

Figure 2.3 shows the L220 Cache Controller MBIST paths for data RAM testing.

Figure 2.3. L220 Cache Controller MBIST paths for data RAM testing

Table 2.4shows the write sequences for data RAM testing.

Table 2.4. Writes for data RAM testing

MBISTADDR[1:0]DATAEN[31:0]DATAWD used
b000x000F[63:0]
b010x00F0[127:64]
b100x0F00[191:128]
b110xF000[255:192]

MBIST Testing of L220 Cache Controller data parity RAM

There is one data parity RAM associated with the L220. Table 2.5 shows the address range of the MBISTADDR bus used to test the data parity RAM, based on the L2 cache size and configured to be 8-way.

Table 2.5. MBISTADDR and MBISTDIN mapping for data parity RAM, 8-way

L2 cache size Number of data RAM indexes MBISTADDR to data parity RAM mapping MBISTDIN to data parity RAM mapping
128KB 4,096 DATAADDR[11:0]=MBISTADDR[17:15,10:2] DATAPWD[31:0]=MBISTDIN[31:0]
256KB 8,192 DATAADDR[12:0]=MBISTADDR[17:15,11:2] DATAPWD[31:0]=MBISTDIN[31:0]
512KB 16,384 DATAADDR[13:0]=MBISTADDR[17:15,12:2] DATAPWD[31:0]=MBISTDIN[31:0]
1MB 32,768 DATAADDR[14:0]=MBISTADDR[17:15,13:2] DATAPWD[31:0]=MBISTDIN[31:0]
2MB 65,536 DATAADDR[15:0]=MBISTADDR[17:2] DATAPWD[31:0]=MBISTDIN[31:0]

The L220 Cache Controller has an LRB, in each slave these are each 256 bits wide. One of these holds data for MBIST testing. The L220 Cache Controller always adds two register delays to the MBIST data read path for the data parity RAM.

When using the L220 MBIST Controller you must account for the data parity RAM latency in the pipeline. The latency can be from one to eight clock cycles. See L220 Compiled RAM Latencies. The signal MBISTCE[10] is for the chip enable to the data parity RAM. The signal MBISTDCTL[12] is for reads from previous MBIST transactions.

Figure 2.4 shows the L220 Cache Controller MBIST paths for data parity RAM testing.

Figure 2.4. L220 Cache Controller MBIST paths for data parity RAM testing

MBIST testing of L220 Cache Controller tag RAMs

There is one Tag RAM for each way of the L2 cache. The maximum number of tag RAMs the MBIST Controller has to test is eight. Only one tag RAM is tested at a time. Table 2.6 shows the address range of the MBISTADDR bus used to test a tag RAM, based on the L2 cache size and configured to be 8-way. The parity for each tag RAM present is tested along with the rest of the tag and is mapped to MBISTDIN[20].

Table 2.6. MBISTADDR and MBISTDIN mapping for tag RAM, 8-way

L2 cache size Number of tag RAM indexes MBISTADDR to tag RAM mapping MBISTDIN to tag RAM mapping
128KB 512 TAGADDR[8:0]=MBISTADDR[10:2] TAGWD[20:0]=MBISTDIN[19:0,20]
256KB 1,024TAGADDR[9:0]=MBISTADDR[11:2] TAGWD[19:0]=MBISTDIN[19:1,20]
512KB 2,048TAGADDR[10:0]=MBISTADDR[12:2] TAGWD[18:0]=MBISTDIN[19:2,20]
1MB 4,096TAGADDR[11:0]=MBISTADDR[13:2] TAGWD[17:0]=MBISTDIN[19:3,20]
2MB 8,192TAGADDR[12:0]=MBISTADDR[14:2] TAGWD[16:0]=MBISTDIN[19:4,20]

Table 2.7 shows the address range of the MBISTADDR bus used to test the tag RAM, based on the L2 cache size and configured to be 4-way.

Table 2.7. MBISTADDR and MBISTDIN mapping for tag RAM, 4-way

L2 cache size Number of tag RAM indexes MBISTADDR to tag RAM mapping MBISTDIN to tag RAM mapping
128KB 4,096TAGADDR[9:0]=MBISTADDR[11:2] TAGWD[19:0]=MBISTDIN[19:1,20]
256KB 8,192TAGADDR[10:0]=MBISTADDR[12:2] TAGWD[18:0]=MBISTDIN[19:2,20]
512KB 16,384TAGADDR[11:0]=MBISTADDR[13:2] TAGWD[17:0]=MBISTDIN[19:3,20]
1MB 2,768TAGADDR[12:0]=MBISTADDR[14:2] TAGWD[16:0]=MBISTDIN[19:4,20]

The data from the tag RAMs is always registered by the L220 Cache Controller, plus there is a register on the MBIST port of the L220 Cache Controller. Consequently, to the L220 MBIST Controller, the L220 always adds two register delays to the MBIST data read path for the tag RAMs.

When using the L220 MBIST Controller you must account for the Tag RAM latency in the pipeline. The signal MBISTCE[8:1] is for chip enables to the tag RAMs. The signal MBISTDCTL[10:3] is for reads from previous MBIST transactions. The latency of the tag RAMs can be from one to eight clock cycles. See L220 Compiled RAM Latencies.

Figure 2.5 shows the L220 Cache Controller MBIST paths for tag RAM testing.

Figure 2.5. L220 Cache Controller MBIST paths for tag RAM testing

Note

  • MBISTCE[8:1] corresponds to TAGCS[7:0]

  • MDBISTDCL[10:3] corresponds to TAG[7:0]

  • Only [20:0] of MBISTDIN and MBISTDOUT are used.

MBIST testing of L220 dirty RAM

There is one dirty RAM associated with the L220 Cache Controller. The dirty RAM uses the same address as the tag RAMs. Table 2.8 shows the address range of the MBISTADDR bus used to test the dirty RAM, based on the L2 cache size and configured to be 8-way.

Table 2.8. MBISTADDR and MBISTDIN mapping for dirty RAM, 8-way

L2 cache size Number of dirty RAM indexes MBISTADDR to dirty RAM mapping MBISTDIN to dirty RAM mapping
128KB 512 TAGADDR[8:0]=MBISTADDR[10:2] DIRTYWD[15:0]=MBISTDIN[15:0]
256KB 1,024TAGADDR[9:0]=MBISTADDR[11:2] DIRTYWD[15:0]=MBISTDIN[15:0]
512KB 2,048TAGADDR[10:0]=MBISTADDR[12:2] DIRTYWD[15:0]=MBISTDIN[15:0]
1M B4,096TAGADDR[11:0]=MBISTADDR[13:2] DIRTYWD[15:0]=MBISTDIN[15:0]
2MB 8,192TAGADDR[12:0]=MBISTADDR[14:2] DIRTYWD[15:0]=MBISTDIN[15:0]

Table 2.9 shows the address range of the MBISTADDR bus used to test the dirty RAM, based on the L2 cache size and configured to be 4-way.

Table 2.9. MBISTADDR and MBISTDIN mapping for dirty RAM, 4-way

L2 cache size Number of Dirty RAM Indexes MBISTADDR to dirty RAM Mapping MBISTDIN to dirty RAM Mapping
128KB 4,096TAGADDR[9:0]=MBISTADDR[11:2] DIRTYWD[15:0]=MBISTDIN[15:0]
256KB 8,192TAGADDR[10:0]=MBISTADDR[12:2] DIRTYWD[15:0]=MBISTDIN[15:0]
512KB 16,384TAGADDR[11:0]=MBISTADDR[13:2] DIRTYWD[15:0]=MBISTDIN[15:0]
1M B2,768TAGADDR[12:0]=MBISTADDR[14:2] DIRTYWD[15:0]=MBISTDIN[15:0]

The data from the dirty RAM is always registered by the L220 Cache Controller, plus there is a register on the MBIST port of the L220 Cache Controller. Consequently, to the L220 MBIST Controller, the L220 always adds two register delays to the MBIST data read path for the dirty RAM.

When using the L220 MBIST Controller you must account for the dirty RAM latency in the pipeline. The signal MBISTCE[9] is for the chip enable to the dirty RAM. The signal MBISTDCTL[11] is for reads from previous MBIST transactions. The latency can be from one to eight clock cycles. See L220 Compiled RAM Latencies.

Figure 2.6 shows the L220 Cache Controller MBIST paths for dirty RAM testing.

Figure 2.6. L220 Cache Controller MBIST paths for dirty RAM testing

Note

  • MBISTCE[9] corresponds to DIRTYCS

  • MBISTDCTL[11] corresponds to the dirty RAM

  • Only [15:0] of MBISTDIN and MBISTOUT are used

  • The dirty RAM uses the same address as the tag RAM.

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