1.1. About the L220 MBIST Controller

MBIST is the industry-standard method of testing embedded memories. MBIST works by performing sequences of reads and writes to the memory according to a test algorithm. Many industry-standard test algorithms exist.

An MBIST Controller generates the correct sequence of reads and writes to all locations of the RAM to ensure that the cells are operating correctly. In doing this, some additional test coverage is achieved in the address and data paths that the MBIST uses. You must only use the L220 MBIST Controller only with the L220 Cache Controller to perform memory testing of the <Level 2> cache RAM.


The example integration files provided with the L220 MBIST Controller only support an 8-way cache design.

MBIST mode takes priority over all other modes for example SCAN, in that the L2 RAMs are only accessible to the L220 MBIST Controller when MBIST mode is activated with the MTESTON pin. You must keep the MTESTON signal LOW during functional mode.

The L220 MBIST Controller controls the MBIST testing of the L2 RAMs through the MBIST port of the L220 Cache Controller. Figure 1.1 shows the L220 Cache Controller MBIST configuration.

Figure 1.1. L220 Cache Controller MBIST configuration

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