A.1. L220 interface signals

Table A.1 shows the L220 MBIST Controller interface signals.

Table A.1. L220 interface

SignalTypeDescription
MBISTDOUT[63:0]Input

MBIST data out, from L220

MBISTDOUT[63:0] = MBIST data out for Data RAM

MBISTDOUT[20:0] = MBIST data out for Tag RAM

MBISTDOUT[15:0] = MBIST data out for Dirty RAM

MBISTDOUT[31:0] = MBIST data out for Data Parity RAM

MBISTADDR[17:0]Output

MBIST address

MBISTADDR[17:0] used for Data RAM, two LSBs used as doubleword select

MBISTADDR[14:2] used for Tag and Dirty RAMs

MBISTADDR[17:2] used for Data Parity RAM

MBISTCE[10:0]Output

MBIST RAM chip enables, for writes

MBISTCE[0] = Data RAM chip enable

MBISTCE[1] = Tag RAM 0 chip enable

MBISTCE[2] = Tag RAM 1 chip enable

MBISTCE[3] = Tag RAM 2 chip enable

MBISTCE[4] = Tag RAM 3 chip enable

MBISTCE[5] = Tag RAM 4 chip enable

MBISTCE[6] = Tag RAM 5 chip enable

MBISTCE[7] = Tag RAM 6 chip enable

MBISTCE[8] = Tag RAM 7 chip enable

MBISTCE[9] = Dirty RAM chip enable

MBISTCE[10] = Data Parity RAM chip enable

MBISTDCTL[12:0]Output

MBIST control, for reads

MBISTDCTL[1:0] = MBIST data select for 64 bits of 256 wide data RAM

MBISTDCTL[2] = MBIST RAM select for Data RAM

MBISTDCTL[3] = MBIST RAM select for Tag RAM 0

MBISTDCTL[4] = MBIST RAM select for Tag RAM 1

MBISTDCTL[5] = MBIST RAM select for Tag RAM 2

MBISTDCTL[6] = MBIST RAM select for Tag RAM 3

MBISTDCTL[7] = MBIST RAM select for Tag RAM 4

MBISTDCTL[8] = MBIST RAM select for Tag RAM 5

MBISTDCTL[9] = MBIST RAM select for Tag RAM 6

MBISTDCTL[10] = MBIST RAM select for Tag RAM 7

MBISTDCTL[11] = MBIST RAM select for Dirty RAM

MBISTDCTL[12] = MBIST RAM select for Data Parity RAM

MBISTDIN[63:0]Output

MBIST Data In, to L220

MBISTDIN[63:0] = MBIST data in for Data RAM

MBISTDIN[20:0] = MBIST data in for Tag RAM

MBISTDIN[15:0] = MBIST data in for Dirty RAM

MBISTDIN[31:0] = MBIST data in for Data Parity RAM

MBISTWEOutputMBIST Write enable
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