3.1. About the MBIST Instruction Register

Figure 3.1 shows the bit fields of the MBIR.

Figure 3.1. MBIST Instruction Register

The MBIR fields set up the behavior of the MBIST engine:

Pattern

Specifies the test algorithm.

Control

Specifies MBIST mode of operation and sticky or nonsticky fail flag.

Write latency

Specifies the number of cycles to enable a RAM write.

Read latency

Specifies the number of cycles to enable a RAM read.

X addr

Specifies the number of bits in the X-address counter.

Y addr

Specifies the number of bits in the Y-address counter.

Data seed

Specifies the four-bit data background.

Enables

Specifies the RAM under test.

Column width

Specifies 4, 8, 16, or 32 columns per block of RAM.

Cache size

Specifies a cache size of 128KB, 256KB, 512KB, 1MB, or 2MB.

Field descriptions describes the MBIR fields in more detail.

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