L220 MBIST Controller Technical Reference Manual 1.2. L220 MBIST Controller interface

1.2. L220 MBIST Controller interface

Figure 1.2 shows the L220 MBIST Controller interface to the Automated Test Equipment (ATE) and to the MBIST interface of the L220 Cache Controller.

Figure 1.2. MBIST Controller wiring diagram

Figure 1.3 shows the traditional method of accessing a cache RAM for MBIST.

Figure 1.3. Traditional method of interfacing MBIST

Because this method significantly reduces the maximum operating frequency, it is not suitable for high-performance designs. Instead, the L220 MBIST Controller uses an additional input to the existing functional multiplexors without reducing maximum operating frequency.

Figure 1.4 shows the five pipeline stages used to access the cache RAM arrays.

Figure 1.4. L220 Cache Controller MBIST interface

The L220 MBIST Controller accesses memory through the MBIST interface of the L220 Cache Controller. Table 1.1 lists the L220 Cache Controller MBIST interface signals.

Table 1.1. L220 Cache Controller MBIST interface signals

Name	Type	Description
nRESET	Input	Global active LOW reset signal.
CLK	Input	Active HIGH clock signal. This clock drives the L220 Cache Controller logic.
MBISTDOUT[63:0]	Output	Data out bus from all cache RAM blocks.
MBISTDCTL[12:0]	Input	Delayed versions of the MBISTCE[10:0] signal and the doubleword select signal, MBISTADDR[1:0]. Selects the correct read data after it passes through the MBIST pipeline stages. MBISTDCTL[12:0] = delayed {MBISTCE[10:0], MBISTADDR[1:0]}.
MTESTON	Input	Select signal for cache RAM array. This signal is the select input to the multiplexors that access the cache RAM arrays for test. When asserted, MTESTON takes priority over all other select inputs to the multiplexors.
MBISTCE[10:0]	Input	One-hot chip enables to select cache RAM arrays for test.
MBISTWE	Input	Global write enable signal for all RAM arrays.
MBISTADDR[17:0]	Input	Address signal for cache RAM array. MBISTADDR[1:0] is the doubleword select value. See Y-address and X-address fields, MBIR[23:20] and MBIR[27:24] for a description of the doubleword select. Not all RAM arrays use the full address width.
MBISTDIN[63:0]	Input	Data bus to the cache RAM arrays. Not all RAM arrays use the full data width.

Note

The interface of the L220 MBIST Controller communicates with both the ATE and the MBIST interface of the L220 Cache Controller. See Appendix A Signal Descriptions for descriptions of the L220 MBIST Controller interface signals. See the L220 Cache Controller Technical Reference Manual for more information about the MBIST interface.

Copyright © 2004-2006 ARM Limited. All rights reserved.	ARM DDI 0330F
Non-Confidential
PDF version