Dynamic low-power mode control operates when the memory controller is in the Ready state.

The functionality that Table 2.5 lists is dependant on whether the memory controller is configured to have a single global cke or a cke per memory device. The functionality works for each cke pin, when using a:

The functionality listed in Table 2.5 is configurable and programmable. A memory controller configuration requires the functionality to be included before it can be enabled through the APB interface.

Table 2.5 lists the dynamic low-power modes operation.

Auto power-down logic negates cke for a memory chip putting the device into either active or precharge power-down mode if a device has been idle for power_down_prd time depending on whether the device had any open rows. The mclk clock decrements the power-down counters. The programmed power_down_prd time must always be greater than the programmed cas latency.

Force precharge logic automatically generates a precharge for an idle activated bank. If a bank has been activated and has executed a data access then subsequently, if no more data accesses are executed for fp_time, then a force precharge is generated to close that idle bank. The aclk clock decrements the force precharge counters.

Auto self-refresh logic operates the same as the auto power-down logic but generates a self-refresh entry for a memory device command instead of negating cke.

Figure 2.21 shows the time after completion of a command to a memory chip until the memory controller puts that chip into power-down mode. Power-down affects all the banks of a chip, therefore there might be cases whereby some banks of a chip enters precharge power-down. However, it would normally be expected for at least one bank to enter active power-down.

Figure 2.22 shows the time after completion of a command to a memory chip until the memory controller places that chip into power-down mode. When fp_enable is set with fp_time set to zero then the equivalent functionality of auto-precharge commands is achieved.

Figure 2.23 shows the time after completion of a command to a memory chip until the memory controller places that chip into precharge power-down mode. To ensure precharge power-down mode for every bank, you must set fp_time to less than power_down_prd - 3 for synchronous 1:1 clocking and scaled accordingly for different clocking modes. For example if mclk is running 2 times slower than aclk then fp_time must be:

((fp_time x 2) + 3) < power_down_prd

When running asynchronously the fp_time must be scaled to ensure it must always be less than the power_down_prd - 3. This ensures that a precharge always occurs before the cke pin is negated.

Figure 2.24 shows the time after completion of a command to a memory chip, until the memory controller places that chip into self-refresh mode. Table 2.5 shows the memory controller can only put a chip into self-refresh mode if the force precharge logic and auto self-refresh logic is configured and enabled. This guarantees that if a self-refresh command is generated all the banks of a chip have been previously precharged. When the auto self-refresh command logic is configured a 10-bit prescalar for each power_down_prd counter is generated. If the prescale value is programmed to zero then the prescalar does not affect the power-down counter.

A prescalar is auto-generated because for some memory types there is a relatively long time for a memory chip to exit self-refresh mode which stalls the command FIFO. Therefore, because the penalty for exiting self-refresh mode is large, you can program a chip select to be idle for a much longer time before entering self-refresh mode when compared to the other power-down modes.