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The memory controller provides architectural support for low-power operation in the following ways:
By using the memc_cmd and memc_status
Registers at address offsets 0x4 and 0x0.
The memory controller can place the SDRAM into the self-refresh
state under software control.
By using the AXI low-power interface, the memory controller can place the SDRAM into the self-refresh state under hardware control.
Additionally, the memory controller microarchitecture provides additional power savings through extensive use of clock gating. This includes clock gating of the external memory clocks by selecting the stop_mem_clock bit in the mem_cfg Register.
You can also implement the memory controller with two power domains:
APB and AXI, aclk
memory, mclk.
See Figure 2.1.
Table 2.3 lists the valid system states of the aclk domain FSM and the mclk domain FSM. It also lists the valid power, clock, and reset states in the aclk and mclk domains. Table 2.3 lists the valid transitions, and the text following it explains how to traverse the system states.
Table 2.3. Valid system states for FSMs
| SDRAM | DMC | System state | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|
| aclk FSM | mclk FSM | |||||||||
| VDD | State | VDD | Clock | Reset | State | VDD | Clock | Reset | State | |
| 0 | Null | 0 | N/a | N/a | Null | 0 | N/a | N/a | Null | 1 |
| 0 | Null | >0 | Running | No | POR | >0 | Running | No | POR | 2 |
| 0 | Null | >0 | Running | Yes | Reset | >0 | Running | Yes | Reset | 3 |
| 0 | Null | >0 | Running | No | Config | >0 | Running | No | Powered_ up | 4 |
| >0 | Accessible | >0 | Running | No | Config | >0 | Running | No | Powered_ up | 5 |
| >0 | Accessible | >0 | Running | No | Ready | >0 | Running | No | Powered_ up | 6 |
| >0 | Powered- down | >0 | Running | No | Ready | >0 | Running | No | Powered_ down | 7 |
| >0 | Self_ refresh | >0 | Running | No | Low_ power | >0 | Running | No | Self_ refresh | 8 |
| >0 | Self_ refresh | >0 | Running | No | Low_ power | >0 | Stopped | No | Self_ refresh | 9 |
| >0 | Self_ refresh | >0 | Stopped | No | Low_ power | >0 | Running | No | Self_ refresh | 10 |
| >0 | Self_ refresh | >0 | Stopped | No | Low_ power | >0 | Stopped | No | Self_ refresh | 11 |
| >0 | Self_ refresh | 0 | N/a | N/a | Null | >0 | Stopped | No | Self_ refresh | 12 |
| >0 | Self_ refresh | 0 | N/a | N/a | Null | >0 | Running | No | Self_ refresh | 13 |
| >0 | Self_ refresh | >0 | Running | No | POR | >0 | Stopped | No | Self_ refresh | 14 |
| >0 | Self_ refresh | >0 | Running | No | POR | >0 | Running | No | Self_ refresh | 15 |
| >0 | Self_ refresh | >0 | Running | Yes | Reset | >0 | Stopped | No | Self_ refresh | 16 |
| >0 | Self_ refresh | >0 | Running | Yes | Reset | >0 | Running | No | Self_ refresh | 17 |
| >0 | Self_refresh | >0 | Stopped | No | Ready | >0 | Stopped | No | Self_refresh | 18 |
The ranking of system power states, from highest power to lowest power, is as follows:
6, 7, 8, 10, 9, 11, 13, 12.
However, states 8-11 are similar and the recommendation is to use state 11 from this group if clock-stopping techniques are available. Similarly, states 12 & 13 are similar and the recommendation is to use state 12 from this pair. Table 2.4 lists a recommended set of power states.
Table 2.4. Recommended power states
| System state | Power name |
|---|---|
| 6 | Running |
| 7 | Auto power-down |
| 11 | Shallow self-refresh or auto self-refresh |
| 12 | Deep self-refresh |
| 18 | Auto self-refresh |
Figure 2.20 highlights these states and arcs.
States 1-5, 9, 14, and 16 are only used as transitional states.
State transitions are as follows:
Apply power to all memory controller power domains, and ensure that aclk and mclk are running.
Assert reset in both the aclk reset domain and the mclk reset domain.
Deassert reset in both the aclk reset domain and the mclk reset domain.
Apply power to the SDRAM power domain.
You must:
Write to all of the memory timing
parameters, address offsets 0x14 to 0x44.
Write to the memory_cfg and refresh_prd Registers,
address offsets 0xC and 0x10.
Initialize the memory, using the direct_cmd Register,
offset 0x8, with the sequence of commands specified
by the memory vendor. When you have sent these commands to the memory,
you can write to the memc_cmd Register, offset 0x4 with
the Go command, 0x0.
Poll the memc_status Register until the value of 0x1 is
returned, Ready, signifying that the memory controller is ready
to accept AXI accesses to the SDRAM.
If you want
to reconfigure either the memory controller or SDRAM, you must first
write to the memc_cmd Register, offset 0x4, with
the Pause command, 0x3, and poll the memc_status
Register until the value of 0x2 is returned,
Paused. Then you can write to the memc_cmd Register with the Configure
command, 0x4 and poll the memc_status Register
until the value of 0x0 is returned, Config.
If auto_power_down is set in the memory_cfg Register, see Memory Configuration Register, then this arc is automatically taken when the SDRAM has been idle for power_down_prd mclk cycles.
When an SDRAM access command has been received in the mclk domain, this arc is taken.
You can take this arc under either hardware or software control:
To take this arc under software control:
Issue the Pause command, or archive the Pause command.
Poll for the Paused state.
Issue the Sleep command.
To take this arc under hardware control, use the AXI low-power interface to request a Low-power state.
The same as arc 6 to 8, but additionally stop the mclk domain clock.
The same as arc 6 to 8, but additionally stop the aclk domain clock.
The same as arc 6 to 8, but additionally stop both the mclk and the aclk domain clocks.
The same as arc 6 to 8, but additionally stop the mclk domain clock and remove power from the aclk power domain. This can only be done if the memory controller implementation has separate power domains for aclk and mclk.
The same as arc 6 to 8, but additionally remove power from the aclk power domain. This can only be done if the memory controller implementation has separate power domains for aclk and mclk.
You can take this arc under either hardware or software control:
To take this arc under software control:
Issue the Wakeup command to the memc_cmd Register.
Poll the memc_status Register for the Paused state.
Issue the Go command and poll for the Ready state.
To take this arc under hardware control, use the AXI low-power interface to bring the memory controller out of a low-power state.
The same as arc 8 to 6, but you must first start the mclk domain clock.
The same as arc 8 to 6, but you must first start the aclk domain clock.
The same as arc 8 to 6, but you must first start both the aclk and mclk domain clocks.
Apply power to the aclk power domain.
Assert reset to the aclk reset domain.
De-assert reset to the aclk reset domain.
Apply power to the aclk power domain.
Assert reset to the aclk reset domain.
De-assert reset to the aclk reset domain.
If auto_power_down
is set in the memory_cfg Register, see Memory Configuration Register, then this arc is automatically taken when
the SDRAM has been idle for power_down_prd mclk cycles. Also requires: fp_line << power_down_prd, fp_enable and sr_enable.
When an SDRAM access command has been received in the mclk domain, this arc is taken.
When power is applied to the aclk domain, when leaving state 1, the memory controller status FSM moves to the Config state. When power is applied to the aclk domain, when leaving states 12 or 13, the memory controller states FSM moves to the Low-power state.
| Copyright © 2004-2007 ARM Limited. All rights reserved. | ARM DDI 0331E |
| Non-Confidential | |
| PDF version | |
| Home > Functional Overview > Low-power operation > System low-power control |