All command control outputs are clocked on the same edge. In Figure 2.6 to Figure 2.17, the control outputs to the external memory are always clocked on the falling edge of the memory clock.
The relative times between control signals from the memory interface are maintained when output from the pad interface to the actual SDRAM devices. Therefore, the timing register values required for a particular SDRAM device can be determined from that SDRAM device’s data sheet. Figure 2.6 to Figure 2.17 show how the data sheet timings map onto the memory controller timing registers.
The times in Figure 2.6 to Figure 2.17 are not necessarily the default timing values, but are values that are small enough to show the entire delay in one figure.
Note
The command_en, data_cntl_en, and read_en signals are internal to the memory controller.
The t_rcd, t_rfc and t_rp have an additional timing parameter called
schedule_rx, defined in their registers. The schedule parameters prevent commands being issued that can stall the command pipeline and are timed in aclk cycles. For synchronized 1:1 operation of aclk and mclk,schedule_rxmust be programmed
to t_rx -3. For non-synchronized 1:1 operation, the value must be scaled accordingly.
Figure 2.6 shows the command control output timing.
Figure 2.7 shows the activate to read or write command timing.
Figure 2.8 shows the bank activate to bank activate or auto-refresh command timing.
Figure 2.9 shows the bank activate to different bank activate for a memory timing.
Figure 2.10 shows the precharge to command and auto-refresh timing.
Figure 2.11 shows activate to precharge, and precharge to precharge timing.
Figure 2.12 shows mode register write to command timing.
Figure 2.13 shows self-refresh entry and exit timing.
Figure 2.14 shows power-down entry and exit timing.
The pwr_down_prd count is timed from the memory interface becoming idle, that is, after a command delay has timed out or the read data FIFO is emptied. cke is asserted when the command FIFO is not empty.
Figure 2.15 shows the turnaround time, tWTR, for the memory interface to output a Write command followed immediately by a Read command.
Figure 2.16 shows the relationship between memory interface outputting the Write command and the WDATA when tDQSS is set to 1. It also highlights the tWR minimum time between a Write and a Precharge command.
Figure 2.17 shows the timing relationship between the Read command being output from the memory interface and the RDATA being returned to the memory interface from the pad interface.
Note
The SDR configuration requires read_delay set to zero.
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