The memory interface provides a clean and defined interface between the pad interface and the arbiter, ensuring that the external memory interface command protocols are met in accordance with the programmed timings in the register block. See Chapter 3 Programmer’s Model.

The external I/Os to this block are:

The memory interface tracks and controls the state of the external memories using either an FSM per extended memory or one FSM depending on the configuration of the memory controller. Figure 2.5 shows the mclk domain FSM.

See Table 2.3 for valid system states and Deep power-down.

The interface is separated from the arbiter using the following configurable synchronous or asynchronous FIFOs:

There is also a static interface which has configuration signals that cannot be changed when the interface is operating.

The memory interface reads commands from the arbiter using a FIFO, but only when that command can be executed. The memory interface ensures a command is only executed when all the inter-command delays, defined in this section, for that bank or chip are met. The memory interface enables multiple banks to be active at any one time. However, only one bank can be carrying out a data transfer at any one time. If the command at the head of the FIFO cannot be executed, then the command pipeline stalls until it can be executed.

The timing parameters in Figure 2.6 to Figure 2.17 can all be programmed using the APB interface. See Chapter 3 Programmer’s Model.