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You can only achieve Deep Power Down (DPD) for individual chips if the memory controller configuration has local cke set, that is, a cke pin for each memory device.
For a memory controller configuration with a global cke it is only possible to enter all the memory devices into the DPD state simultaneously.
To ensure that no refreshes are generated for a chip select that has been put into DPD mode, the active_chips bits must be reduced in line with the DPD commands. This means that DPD mode can only be entered from the most significant chip select of a configuration downwards.
The system architect must ensure that no data transactions are sent to a chip select that has been entered into DPD mode.
The flow for entering power-down mode is as follows:
Enter Pause state.
Enter Low-power state.
Write a direct command to the highest chip select number configured with a PRECHARGEALL command, so as to only enter DPD with all chips precharged.
Write a direct command to the highest chip select number configured with a DPD command.
Write direct command to the next highest chip select number if required.
Write to the active_chips bits of the memory_configuration register to disable refreshes for the power-down chip selects.
To remove a chip select from DPD is the reverse of the above sequence, excluding the PRECHARGEALL command.
A chip select must have the active_chips bits set before providing the NOP direct command and then carrying out the memory initialization sequence.
All the registers are available for writes or reads when the FSM is in the Config or Low-power state.
| Copyright © 2004-2007 ARM Limited. All rights reserved. | ARM DDI 0331E |
| Non-Confidential | |
| PDF version | |
| Home > Functional Overview > Low-power operation > Deep power-down |