PrimeCell® Dynamic Memory Controller (PL340) Technical Reference Manual 3.2. Register summary

3.2. Register summary

Figure 3.2 shows the memory controller configuration register map.

Figure 3.2. Memory controller configuration register map

Figure 3.3 shows the AXI ID configuration registers map.

Figure 3.3. AXI ID configuration register map

Figure 3.4 shows the chip configuration register map.

Figure 3.4. Chip configuration registers map

Figure 3.5 shows the identification register map.

Figure 3.5. Identification register map

Table 3.1 lists the memory controller registers.

Table 3.1. Memory controller register summary

Name	Base offset	Type	Reset value	Description
memc_status	`0x000`	RO	-^[1]	Memory Controller Status Register
memc_cmd	`0x004`	WO	-	Memory Controller Command Register
direct_cmd	`0x008`	WO	-	Direct Command Register
memory_cfg	`0x00C`	RW	`0x00010020`	Memory Configuration Register
refresh_prd	`0x010`	RW	`0x00000A60`	Refresh Period Register
cas_latency	`0x014`	RW	`0x00000006`	CAS Latency Register
t_dqss	`0x018`	RW	`0x00000001`	t_dqss Register
t_mrd	`0x01C`	RW	`0x00000002`	t_mrd Register
t_ras	`0x020`	RW	`0x00000007`	t_ras Register
t_rc	`0x024`	RW	`0x0000000B`	t_rc Register
t_rcd	`0x028`	RW	`0x0000001D`	t_rcd Register
t_rfc	`0x02C`	RW	`0x00000212`	t_rfc Register
t_rp	`0x030`	RW	`0x0000001D`	t_rp Register
t_rrd	`0x034`	RW	`0x00000002`	t_rrd Register
t_wr	`0x038`	RW	`0x00000003`	t_wr Register
t_wtr	`0x03C`	RW	`0x00000002`	t_wtr Register
t_xp	`0x040`	RW	`0x00000001`	t_xp Register
t_xsr	`0x044`	RW	`0x0000000A`	t_xsr Register
t_esr	`0x048`	RW	`0x00000014`	t_esr Register
memory_cfg2	`0x04C`	RW	`-`^[2]	memory_cfg2 Register
memory_cfg3	`0x050`	RW	`0x00000006`	memory_cfg3 Register
-	`0x054-0x0FC`	-	-	-
id_n_cfg	`0x100`	RW	`0x00000000`	id_<n>_cfg Registers
chip_n_cfg	`0x200`	RW	`0x0000FF00`	chip_<n>_cfg Registers
user_status	`0x300`	RO	-	user_status Register
user_config	`0x304`	WO	-	user_config Register
periph_id_n	`0xFE0`-`0xFEC`	RO	-	Peripheral Identification Registers 0-3
pcell_id_n	`0xFF0`-`0xFFC`	RO	-	PrimeCell Identification Registers 0-3
^[1]Dependent on configuration. ^[2]Dependent on tie-off port values.

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