PrimeCell® Dynamic Memory Controller (PL340) Technical Reference Manual 3.3.2. Memory Controller Command Register

3.3.2. Memory Controller Command Register

The write-only memc_cmd Register enables the memory controller to be traversed. The command register controls the programmer’s view FSM. By writing to this register, the FSM can be traversed. If a new command is received to change state, and a previous command to change state has not completed, the pready signal is held LOW until the new command can be carried out.

Figure 3.7 shows the register bit assignments.

Figure 3.7. memc_cmd Register bit assignments

Table 3.4 lists the register bit assignments.

Table 3.4. memc_cmd Register bit assignments

Bits	Name	Function
[31:3]	-	Undefined. Write as zero.
[2:0]	memc_cmd	Changes the state of the memory controller: 3’b000 = Go 3’b001 = Sleep 3’b010 = Wakeup 3’b011 = Pause 3’b100 = Configure 3'b111 = Active_Pause.

Bits

Name

Function

[31:3]

Undefined. Write as zero.

[2:0]

memc_cmd

Changes the state of the memory controller:

3’b000 = Go

3’b001 = Sleep

3’b010 = Wakeup

3’b011 = Pause

3’b100 = Configure

3'b111 = Active_Pause.

Note

Active_Pause puts the memory controller into the Paused state without draining the arbiter queue. This enables you to enter low-power mode to change configuration settings such as memory frequency or timing register values without requiring coordination between masters in a multi-master system.

If the memory controller is put into low-power mode after using the Active_Pause command, you must not remove power from the memory controller because this results in data loss and violation of the AXI protocol. The memory controller does not issue refreshes while in the Config state. You must use low-power mode to make register updates because this ensures that the memory is put into self-refresh rather than entering the Config state when the memory contains valid data.

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