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The write-only direct_cmd Register passes commands to the external memory. The configuration of the direct_cmd Register enables you to write to any type of Mode register supported by the external memory device, and also to generate NOP, Prechargeall, and Auto-refresh commands.
The direct_cmd Register therefore enables any initialization sequence that an external memory device might require. The only timing information associated with the direct_cmd Register are the command delays defined in the timing registers. Therefore, if an initialization sequence requires additional delays between commands, they must be timed by the master driving the initialization sequence.
This register can only be written to in the Config or Low-power state. Figure 3.8 shows the register bit assignments.
Table 3.5 lists the register bit assignments.
Table 3.5. direct_cmd Register bit assignments
Bits | Name | Function |
|---|---|---|
[31:23] | - | Undefined, write as zero |
| [22] | ext_mem_cmd | Extended memory command, see note after the table |
| [21:20] | chip_nmbr | Bits mapped to external memory chip address bits |
| [19:18] | memory_cmd | Determines the command required, see note after the table |
| [17:16] | bank_addr | Bits mapped to external memory bank address bits when command is Modereg access |
| [15:14] | - | Undefined, write as zero |
[13:0] | addr_13_to_0 | Bits mapped to external memory address bits [13:0] when command is Modereg access |
Memory command encoding uses the ext_mem_cmd bits concatenated to memory_cmd, therefore providing 3 bits as follows:
3’b000 = Prechargeall
3’b001 = Autorefresh
3’b010 = Modereg or Extended modereg access
3’b011 = NOP, for SDRAM only
If you have the NVM plug-in licensed, do not use the NOP command with NVM chip selects.
3’b100 = DPD
All other combinations are illegal and might cause undefined behavior.
A NOP command asserts all chip selects that are set as active_chips when the chip_nmbr is set to 0.
If chip_nmbr is set to 1 only cs_n[1] is asserted.
If chip_nmbr is set to 2 only cs_n[2] is asserted.
If chip_nmbr is set to 3 only cs_n[3] is asserted.
| Copyright © 2004-2007 ARM Limited. All rights reserved. | ARM DDI 0331F |
| Non-Confidential | |
| PDF version | |
| Home > Programmer’s Model > Register descriptions > Direct Command Register |