PrimeCell® Dynamic Memory Controller (PL340) Technical Reference Manual 3.3.6. CAS Latency Register

3.3.6. CAS Latency Register

The read/write cas_latency Register sets the CAS latency in memory clock cycles. It can only be read from and written to in the Config or Low-power state. Figure 3.11 shows the register bit assignments. See also Memory interface.

Note

You are required to match the programmed cas latency with the cas latency written to the memory device through the direct_cmd Register.

Figure 3.11. cas_latency Register bit assignments

Table 3.8 lists the register bit assignments.

Table 3.8. cas_latency Register bit assignments

Bits	Name	Function
[31:4]	-	Read undefined, write as zero.
[3:1]	cas_latency	CAS latency in memory clock cycles.
[0]	cas_half_cycle	Encodes whether the CAS latency is half a memory clock cycle more than the value given in bits [3:1]: 1’b0 = Zero cycles offset to value in [3:1]. b0 is forced to 0 in Mobile DDR, SDR, and eDRAM mode. 1’b1 = Half cycle offset to value in [3:1].

Bits

Name

Function

[31:4]

Read undefined, write as zero.

[3:1]

cas_latency

CAS latency in memory clock cycles.

[0]

cas_half_cycle

Encodes whether the CAS latency is half a memory clock cycle more than the value given in bits [3:1]:

1’b0 = Zero cycles offset to value in [3:1]. b0 is forced to 0 in Mobile DDR, SDR, and eDRAM mode.

1’b1 = Half cycle offset to value in [3:1].

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