PrimeCell® Dynamic Memory Controller (PL340) Technical Reference Manual 3.3.1. Memory Controller Status Register

3.3.1. Memory Controller Status Register

The read-only memc_status Register provides information on the configuration of the memory controller, and also on the current state of the memory controller. It cannot be read in either the Reset or POR states. Figure 3.6 shows the register bit assignments.

Figure 3.6. memc_status Register bit assignments

Table 3.2 lists the register bit assignments.

Table 3.2. memc_status Register bit assignments

Bits	Name	Function
[31:13]	-	Read undefined.
[12:]	memory_banks1	This returns part of the definition of the number of banks that the PL340 supports on each chip.^[1]
[11:10]	exclusive_monitors	Returns the number of exclusive access monitor resources implemented in the memory controller: 2’b00 = 0 monitors 2’b01 = 1 monitor 2’b10 = 2 monitors 2’b11 = 4 monitors.
[9]	memory_banks0	This returns part of the definition of the number of banks that the PL340 supports on each chip.^a
[8:7]	memory_chips	Returns the number of different chip selects that the memory controller supports: 2’b00 = 1 chip 2’b01 = 2 chips 2’b10 = 3 chips 2’b11 = 4 chips.
[6:4]	memory_type	Returns the SDRAM that the memory controller supports: 3’b000 = SDR SDRAM 3’b001 = DDR SDRAM 3’b011 = Mobile DDR SDRAM 3’b010 = eDRAM 3’b1xx = Reserved. If Mobile DDR SDRAM or SDR SDRAM or an eDRAM is supported, the cas_half_cycle bit at address offset `0x14` is ignored.
[3:2]	memory_width	Returns the width of the external memory: 2’b00 = 16-bit 2’b01 = 32-bit 2’b10 = 64-bit 2’b11 = Reserved.
[1:0]	memc_status	Returns the state of the memory controller: 2’b00 = Config 2’b01 = Ready 2’b10 = Paused 2’b11 = Low_power.
^[1]See Table 3.3 for memory banks chip configuration information.

Table 3.3 lists the memory banks chip configurations.

Table 3.3. Memory banks chip configuration

Memorybanks1 and Memorybanks0	Banks per memory chip
0	4
1	2^[1]
2	Reserved
3	Reserved
^[1]Two memory banks per chip is applicable for only eDRAM configurations.

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