Using the programmed values in the chip_<n>_cfg Registers that Chapter 3 Programmer’s Model defines, an incoming address has the most significant eight address bits compared with the address match bits using the address mask to ignore any don't care bits to select an external chip.

The transfer is still carried out if there is no match, but the result is undefined.

The AXI address determines the row address using bits [5:3] of the memory_cfg Register, and also the brc_n_rbc bit for the selected chip defined in the chip_<n>_cfg Register.

The AXI address determines the column address using bits [2:0] of the memory_cfg Register.

The AXI address determine the chip bank depending on the configuration of the PL340 in addition to the brc_n_rbc bit for the selected chip defined in the chip_<n>_cfg register.